Detailed answers on the principle of asynchronous reset synchronous release

First of all, I find the principle of network asynchronous reset synchronous release of relevant information. Most do not make it clear what the principle of correlation, it is annoying.

 

Now spent a day time principle answer: to understand why asynchronous reset, synchronous release can be achieved?

 

Reset operation principle must first know the D flip-flop, a reset signal is applied to the last port acts on the intermediate trigger logic.

When the reset terminal active (usually 1), a reset signal is directly applied to the last stage of the SR latch (latch needs to know the principles and the principles of the flip-flop, which is the basis of electrons), then the flip-flop directly q is 0 output.

When the reset signal is inactive (0), the reset signal is 0, the drive is not the last stage of the SR latch, then the output of the input q = d, where by a common clock signal and reset signal control data changes, so that q = d.

When the graph set, are reset terminal CLR of FIG, we understand, it is understood that separate set.

Asynchronous reset, synchronous release.

Module1 code (CLK, RST_N, rst_n_out);
 INPUT CLK;
 INPUT RST_N;
 Output rst_n_out; 

// wire rst_n_out_n;    // O type is not defined, the default type is wire 
REG rst_n1;
 REG rst_n2; 

Always @ ( posedge CLK or  negedge RST_N )
 the begin 
    IF ! ( RST_N) 
        the begin 
     rst_n1 <= . 1 ' B0; 
     rst_n2 <= . 1 ' B0; 
       End 
     the else  
       the begin 
       rst_n1 <= . 1 'b1;
       rst_n2 <= rst_n1;
        end
end
    
assign rst_n_out = rst_n2;

endmodule

 

Rst_n first to 0, that is, a reset terminal (starting at this time as a reset state), then q1 and q2 rst_n simultaneously controlled by the reset signal, 0 is output directly.

When rst_n process goes from 01, the reset terminal becomes 0 at this time, it will not effect the output of direct flip-flop. At this state, q1 is determined by d1, q2 is determined by d2. At this time, since the clock edge q1 have a common effect of the first flip-flop reset signal

Since d1 is, q1 will be determined according to the output CLK, the clock time due to the reset signal has been applied to the second flip-flop, d2 is the case before the state q1 = 0, d2 is 0 since, according to the D flip-flop principle, regardless of clk Why, q2 = 0, so the output is 0 q2 continue.

 

When the recovery time of the first flip-flop reset signal and the clock signal is not satisfied, i.e., it does not satisfy the trigger internal delay of the first stage, this time, the first flip metastable state occurs, but this time the second stage trigger has finished rising,

We need to wait for the next rising edge of the data in order to continue to change q2.

 

When the metastable time elapses (metastability no longer than one cycle, more than one cycle will still affect the second stage flip-flop), the next clock period comes, the normal case have a first flip-flop output 1, and the second flip-flop can be directly equal to d2, the output time rst_n_out = 1, the reset is completed.

 

That is asynchronous reset, synchronous nature is released, the original can act directly upon the active asynchronous reset signal to the output terminal, instead delayed by a clock cycle controlling the reset signal is invalid, i.e., the synchronization is released.