[FPGA] Verilog basic circuit design guide

Writing time: 2020-10-31

Contents:
Design Fundamentals and most 1. Typical circuit
-1.1 full adder
-1.2 datapath
-1.3 counter
-1.4 arithmetic operations
-1.5 logical operations
-1.6 shift operations
-1.7 operation timing
-1.8 the ALU
-1.9 FSM
- 1.10 Tri-state bus
2. Common circuit design (need to fully understand)
-2.1 CRC check code generator
-2.2 Random number generation
-2.3 Dual-port RAM
-2.4 Synchronous FIFO
-2.5 Asynchronous FIFO

Learning idea:
first learn the basic modules, and then understand and digest them, it is the foundation. Then learn some common circuits, and then you can slowly design the project.

Main text:
1. The design and the most basic knowledge of typical circuit-1.1
Full adder

module FULLADDR(Cout, Sum, Ain, Bin, Cin);
input Ain, Bin, Cin;
output Sum, Cout;
wire Sum;
wire Cout;
assign Sum = Ain ^ Bin ^ Cin;
assign Cout = (Ain & Bin) | (Bin & Cin) | (Ain & Cin);
endmodule

-1.2 Data path-
1.2.1 Multiplexer selecting one of four

//Example of a mux4-1.
module MUX( C,D,E,F,S,Mux_out);
input C,D,E,F ; //input
input [1:0] S ; //select control
output Mux_out ; //result
reg Mux_out ;
//mux
always@(C or D or E or F or S)
begin
 case (S)
2'b00 : Mux_out = C ;
2'b01 : Mux_out = D ;
2'b10 : Mux_out = E ;
default : Mux_out = F ;
 endcase
end

-1.2.2 Decoder

//Example of a 3-8 decoder
module DECODE(Ain,En,Yout);
input En ; //enable
input [2:0] Ain ; //input code
output [7:0] Yout ;
reg [7:0] Yout ;
always@(En or Ain)
begin
if(!En)
Yout = 8'b0 ;
else
case (Ain)
3'b000 : Yout = 8'b0000_0001 ;
3'b001 : Yout = 8'b0000_0010 ;
3'b010 : Yout = 8'b0000_0100 ;
3'b011 : Yout = 8'b0000_1000 ;
3'b100 : Yout = 8'b0001_0000 ;
3'b101 : Yout = 8'b0010_0000 ;
3'b110 : Yout = 8'b0100_0000 ;
3'b111 : Yout = 8'b1000_0000 ;
default : Yout = 8'b0000_0000 ;
endcase
end
endmodule

-1.3 Counter

在这里插入代码片

-1.4 Arithmetic operation
-1.5 Logic operation
-1.6 Shift operation
-1.7 Sequential operation
-1.8 ALU
-1.9 Finite state machine-
1.10 Three-state bus

1.2 Data Path

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THE END~