Table of contents
1. Hardware schematic analysis
2. Analysis of IO multiplexing registers
3.2 I2C1_IADR (set slave address)
3.3 I2C1_IFDR (set frequency division value)
3.4 I2C1_I2CR (I2C enable, interrupt control)
3.5 I2C1_I2SR (save communication status)
3.6 I2C1_I2DR (data transmission/reception)
1. Function selection (0x00 — bit2:0)
1. Hardware schematic analysis
I2C mainly involves two pins, namely SCL and SDA. Since it involves IO, it is necessary to know which two pins can be multiplexed as SCL and SDA.
First look at the I2C module on the backplane. We found that IMX.6ULL has two I2C controllers, namely I2C1 and I2C2. Suppose we want to use I2C1.
Then look at which pins on the core board the I2C module on the bottom board is connected to.
The last is to find the multiplexing registers related to UART4_TXD and UART4_RXD.
① TXD related (multiplexed as SCL)
- IOMUXC_SW_MUX_CTL_PAD_UART4_TX_DATA
- IOMUXC_SW_PAD_CTL_PAD_UART4_TX_DATA
② RXD related (multiplexed as SDA)
- IOMUXC_SW_MUX_CTL_PAD_UART4_RX_DATA
- IOMUXC_SW_PAD_CTL_PAD_UART4_RX_DATA
2. Analysis of IO multiplexing registers
IO initialization involves two aspects, one is to specify which function to multiplex, and the other is to configure the electrical properties of the multiplexed pins. The initial value of the electrical properties is the same as before, set to 0x10B0.
- I/O multiplexing
- IOMUXC_SW_ MUX _CTL_PAD_UART4_TX_DATA ( multiplexed as SCL )
- IOMUXC_SW_MUX_CTL_PAD_UART4_RX_DATA (multiplexed as SDA )
- Configure Electrical Properties
- IOMUXC_SW_ PAD _CTL_PAD_UART4_TX_DATA (initial value is 0x70B0)
- IOMUXC_SW_ PAD _CTL_PAD_UART4_RX_DATA (initial value is 0x70B0)
/*************** SCL复用初始化 ******************/
寄存器(基地址): IOMUXC_SW_MUX_CTL_PAD_UART4_TX_DATA (0x20E00B4)
寄存器(基地址): IOMUXC_SW_PAD_CTL_PAD_UART4_TX_DATA (0x20E0340)
初始化操作:
IOMUXC_SW_MUX_CTL_PAD_UART4_TX_DATA &=~ (0xF); // 低4位清零
IOMUXC_SW_MUX_CTL_PAD_UART4_TX_DATA |= 1; // 复用为I2C1_SCL
IOMUXC_SW_PAD_CTL_PAD_UART4_TX_DATA = 0x70B0;
/*************** SDA复用初始化 ******************/
寄存器(基地址): IOMUXC_SW_MUX_CTL_PAD_UART4_RX_DATA (0x20E00B8)
寄存器(基地址): IOMUXC_SW_PAD_CTL_PAD_UART4_RX_DATA (0x20E0344)
初始化操作:
IOMUXC_SW_MUX_CTL_PAD_UART4_RX_DATA &=~ (0xF); // 低4位清零
IOMUXC_SW_MUX_CTL_PAD_UART4_RX_DATA |= 1; // 复用为I2C1_SDA
IOMUXC_SW_PAD_CTL_PAD_UART4_RX_DATA = 0x70B0;3. I2C register analysis
3.1 Clock configuration
This register has already been configured when learning CCM to configure clock frequency. When CSCMR1[PERCLK_PODF] is configured as divide by 1, IPG_CLK_ROOT = PERCLK_CLK_ROOT = 66 MHz.
Configuration method reference: IPG_CLK configuration
3.2 I2C1_IADR (set slave address)
If the current device is a slave, the I2C1_IADR register needs to be set. If the current device is a host, the I2C1_I2DR register is set.
寄存器: I2C1_IADR
基地址: 0x21A0000
地址设置:
I2C1_IADR = 0; // 地址清零
I2C1_IADR |= address; // address 表示从机地址3.3 I2C1_IFDR (set frequency division value)
The frequency can be divided again inside the I2C controller, the clock source is PERCLK_CLK_ROOT = IPG_CLK_ROOT = 66 MHz. In standard mode, the I2C transmission speed can reach up to 100 kbit/s, then the frequency division number = 66000000 / 100000 = 660
We want to find the frequency division number closest to 660 in the table below, we found that the closest is 640, so the value to be set in the register can be 0x15, 0x38
寄存器: I2C1_IFDR
基地址: 0x21A0004
地址设置:
I2C1_IFDR = 0x15; // 分频值为 640 3.4 I2C1_I2CR (I2C enable, interrupt control)
bit 2: Generate a repeated start. Generally, the host is used to modify the communication direction or communication address. If the bus is already occupied, but not occupied by the current device, it cannot send at this time (0: no repeated start 1: generate a repeated start)
bit 3: Send a reply. (0: send a response, equivalent to ACK=0 1: do not send a response, equivalent to ACK=1)
bit 4: Set the communication direction. The essence is to indicate whether to read data to the DR register or write data to the DR register (0: receive (read) 1: send (write))
bit 5: Whether the current device is a master or a slave. Once this bit is set to 1, it is equivalent to sending a start signal to occupy the main line. If multiple hosts participate in the bus occupation, arbitration will occur. If the current device fails to arbitrate, the current bit will be cleared (0: slave 1: host)
bit 6: I2C interrupt enable (0: disable 1: enable)
bit 7: I2C enable (0: disable 1: enable)
// 一开始不会初始化所有的位，一些位只有在实际使用才会被设置
寄存器: I2C1_I2CR
基地址: 0x21A0008
相关操作:
/*
* 发送开始信号（抢占总线，让自己成为主机）
* bit 4: 1 发送
* bit 5: 1 主机
*/
I2C1_I2CR |= ((1 << 4) | (1 << 5));
/*
* 发送重复开始信号（总线已经被占用，而且必须是当前设备占用总线，才能发送重复开始信号）
* bit 2: 1 产生一次重复开始信号
* bit 4: 1 发送
*/
I2C1_I2CR |= ((1 << 2) | (1 << 4));
/*
* 产生一个停止信号
* bit 3: 0 产生一个ACK
* bit 4: 0 接收（要产生一个ACK，当前设备必须为接收模式）
* bit 5: 0 从机
*/
I2C1_I2CR &= ~((1 << 3) | (1 << 4) | (1 << 5));3.5 I2C1_I2SR (save communication status)
bit 0: ACK/NACK received (0: ACK received 1: NACK received)
bit 1: Whether there is an I2C interrupt pending. The following are three situations that trigger interrupts (0: no interrupt pending 1: interrupt pending)
- A byte of data transfer is complete
- In the mode of receiving from the slave, it matches the address sent by the master
- Arbitration failure, loss of bus occupancy
bit 2: current communication direction (0: slave receives, master sends 1: slave sends, master receives)
bit 4: Whether the arbitration has failed. Different from bit 5 of the above I2CR, here is purely to obtain the arbitration result.
The following three situations will be judged as arbitration failure. The state of this bit is controlled by hardware and cannot be set by software (0: arbitration has not failed 1: arbitration has failed and lost control of the main line)
- When the bus is occupied, send a start signal
- The current device is a slave, request to restart
- The host did not send a stop signal, but it detected a stop signal
bit 5: Whether the I2C bus is idle (0: the bus is idle 1: the bus is occupied)
bit 6: Whether the current device is a slave. If the current device is a slave, it is necessary to obtain the current communication direction according to bit 2 of the I2SR, and set the corresponding bit of the I2CR register, that is, bit 4 (0: the current device is not positioned 1: the current device is designated as a slave)
bit 7: Current data transmission status. In fact, it is to judge whether the DR register can be used for the next transmission. (0: data transmission 1: transmission is completed, it will be set to 1 when the falling edge of the ninth cycle of the clock occurs)
Note: For each transmission of data, whether it is sending or receiving, before using the DR register, you need to wait for the DR register to be available, similar to an initialization operation.
- bit 1: Whether the data transfer is complete
- bit 7: Whether the DR register can be used for the next transmission
寄存器: I2C1_I2SR
基地址: 0x21A000C
3.6 I2C1_I2DR (address/data transfer)
If the current device is the receiver, this register stores the received data; if the current device is the sender, this register stores the data to be sent.
寄存器: I2C1_I2DR
基地址: 0x21A0010
4. Analysis of AP3216C
AP3216C is a three-in-one integrated module, integrating ALS (light sensor), PS (proximity sensor), IR (infrared LED), compatible with I2C interface.
The AP3216C reference manual gives the system registers and the detailed register configuration of each module of ALS, PS, and IR. The system configuration is mainly about which modules to enable and the data obtained by different modules; To view the detailed register configuration of each module.
1. Function selection (0x00 — bit2:0)
The System Configure register occupies one byte, the address is 0x00
Among them, bit 2:0 can control the opening and closing of the three modules
2、IR + PS
IR is generally used with PS, IR data occupies 10 bits, and PS data also occupies 10 bits.
① IR Data: It saves the infrared light intensity in the current environment. The register size of 0x0A and 0x0B is one byte
② PS Data: Save the current position of the object. The register size of 0x0E and 0x0F is one byte
3、IF
ALS data occupies 16 bits, which saves the ambient light intensity. The register size of 0x0C and 0x0D is one byte
