table of Contents
3.3 Transmission 1 byte format
3.4 Acknowledgement (ACK) and non-acknowledgement (NACK)
3.5 Slave device address and read and write bits
2. Introduction to EEPROM (AT24C64)
2. EEPROM read and write timing
1. I2C communication protocol
1.I2C bus introduction
The I2C bus is a simple, two-way two-wire synchronous serial bus developed by Philips . It only needs two wires to transfer information between devices connected to the bus.
The master device is used to start the bus to transmit data and generate a clock to open the device for transmission. At this time, any addressed device is regarded as a slave device. The relationship between master and slave, sending and receiving on the bus is not constant, but depends on the data transfer direction at this time. If the host wants to send data to the slave device, the host first addresses the slave device, then actively sends the data to the slave device, and finally the host terminates the data transfer; if the host wants to receive data from the slave device, the master device first addresses the slave device. Then the host receives the data sent from the device, and finally the host terminates the receiving process. under these circumstances. The host is responsible for generating the timing clock and terminating data transmission.
The I2C bus is a recognized world standard. More than 50 companies produce integrated circuits implemented in more than 1,000 different places. In addition, the general i2c bus is used in various control architectures, such as System Management Bus (SMBus), Power Management Bus (PMBus), Intelligent Platform Management Interface (IPMI), Display Data Channel (DDC) and Advanced Telecom Computing Architecture (ATCA) ).
2. I2C bus characteristics
- Only two buses are needed: serial data line (SDA) and serial clock line (SCL);
- Each device connected to the bus is addressed by a software with a unique address and a simple master/slave relationship;
- It is a true multi-master bus. If two or more masters initiate data transmission at the same time, it comes with collision detection and arbitration to prevent data damage;
- Serial, 8-bit, two-way data transmission, up to 100kbit/s in standard mode, 400kbit/s in fast mode, and 1mbit/s in fast mode+. In addition, it can reach up to 100kbit/s in high-speed mode. Up to 3.4 Mbit/s;
- Serial, 8-bit, unidirectional data transmission up to 5mbit/s in ultra-fast mode;
- On-chip filtering rejects spikes on the bus data line to maintain data integrity;
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The number of integrated circuits that can be connected to the same bus is only limited by the maximum bus capacitance. Under certain conditions, more capacitance can be allowed.
The following figure shows an example of I2C bus application:
It can be seen that a lot of I2C bus devices are connected to the two buses of SDA and SCL, and data is transmitted through the I2C bus at a time. The bus topology diagram connected with FPGA is as follows:
3. I2C bus protocol
The two-wire serial data line (SDA) and serial clock (SCL) transfer information between devices connected to the bus. Each device has a unique address (whether it is a microcontroller, LCD driver, memory or keyboard interface), which can operate as a transmitter or receiver according to the function of the device. An LCD driver may be just a receiver, and the memory can receive and transmit data. In addition to the transmitter and receiver, the device can also be considered as a master device or a slave device when performing data transmission.
The figure below shows an example of an i2c bus configuration using two microcontrollers. This example highlights the master-slave relationship and the receive-send relationship found on the i2c bus. Note that these relationships are not permanent, but only depend on the direction of data transmission at the time.
The master device is always responsible for the generation of the clock signal on the i2c bus; when data is transmitted on the bus, each master device generates its own clock signal. The bus clock signal will only change when the clock line is pulled down by the low slave or arbitrated by another master.
3.1 SDA and SCL signals
Both SDA and SCL are bidirectional lines, connected to a positive supply voltage through a current source or pull-up resistor (as shown in the figure below). The output stage of the device connected to the bus must have an open drain or open collector to perform the line sum function. Data on I2C-bus can be transmitted at a rate of up to 100kbit/s in standard mode, at a rate of up to 400kbit/s in fast mode, 1 Mbit/s in fast mode +, and up to 1 Mbit/s in high-speed mode 3.4 Mbit/s. Bus capacitance limits the number of interfaces connected to the bus.
3.1 Data validity
The data on the SDA line must remain stable during the high clock period. Only when the clock signal on the SCL line is low, the high or low state of the data line can be changed
(see the figure below). A clock pulse is generated for each data bit transmitted. Therefore, when designing the signal, the best situation is that the data on the SDA data line changes when the clock line scl is in the middle of the low level, and the data on the SDA data line is obtained when the clock line is in the middle of the high level.
3.2 Start and stop bits
All data transmission starts with START (S) and ends with STOP (P) (see the figure below).
I2C bus idle: SDA and SCL are both high;
I2C protocol start bit: when SCL is high, SDA has a falling edge;
I2C protocol stop bit: when SCL is high, SDA has a rising edge.
Start and stop conditions are always generated by the master device. After the start condition, the bus is considered busy. The bus is idle again for a certain period of time after the stop condition. If a repeated start (Sr) is generated instead of a stop condition, the bus will remain busy. In this regard, the start (S) and repeated start (Sr) conditions are functionally the same.
3.3 Transmission 1 byte format
The length of each byte transmitted on the SDA data line must be 8 bits. The number of bytes that can be transmitted per transmission is unlimited. Each byte must be followed by an acknowledge bit (ACK). The data is transmitted from the most significant bit (MSB) of the byte (see the figure below). If a slave device cannot receive or send another complete byte of data until it performs some other functions, such as servicing internal interrupts, it can keep the clock line scl low and force the master device to enter the waiting state. When the slave device is ready for another byte of data, it continues to transmit data and releases the clock line SCL.
3.4 Acknowledgement (ACK) and non-acknowledgement (NACK)
The response occurs after each byte. The acknowledge bit responds, indicating that the byte has been successfully received and another byte can be sent. The master device generates all clock pulses, including the ninth clock pulse of the acknowledge bit. The response signal is defined as follows: During the response to the clock pulse, the transmitter releases the SDA line, and the receiver can pull the SDA line low and keep it low during the high level of the clock.
When SDA remains high during the 9th clock pulse, this is defined as a non-acknowledgment signal. Then, the master device can generate a stop condition to terminate the transmission, or generate a repeated start condition to start a new transmission. There are five conditions for generating NACK:
- There is no receiver with the transmitted address on the bus, so there is no device to answer.
- The receiver cannot receive or send because it is performing some real-time functions and is not ready to start communicating with the master.
- During the transmission process, the receiver obtains data or commands that it does not understand.
- During the transmission, the receiver cannot receive more data bytes.
- The master receiver must send the end of transmission signal to the slave transmitter.
3.5 Slave device address and read and write bits
The slave device address is the basis for the I2C protocol to address the devices on the bus when transmitting data. Data transmission follows the format shown in the figure below. After the start condition, send a slave device address. This address is 7 bits long, followed by a data direction bit (R/W)-"0" means transmission (write), and "1" means data request (read) (see the following figure 2). Data transmission always ends with a stop condition (P) generated by the master device. However, if a master still wants to communicate on the bus, it can generate a repeated start condition (Sr) and address without generating a stop condition.
The slave device address is usually a combination of fixed and variable bits. The so-called fixed position is the device that is determined to be unchangeable and is considered uncontrollable, while the variable bit is usually the hardware of the device, which can be used for hardware connection by the user. It is determined according to the user's hardware connection. For example, the 7-bit device in the figure below In the address, the first four digits 1010 are fixed at the factory, and the last three digits are the device hardware pins for users to change.
For different devices, the I2C transmission format is slightly different. For storage devices, it also has the address number of the memory. After the master device sends the device address and the slave device memory responds, the master device must send another 8 or 16-bit memory address data. After selecting the memory address and waiting for the response from the slave device, the master device is sending data to or reading data from the memory address.
The above description of the I2C protocol refers to the UM10204 I2C-bus specification and user manual Rev. 4-13 February 2012 ( i2c bus specification and user manual ) of
NXP Semiconductors . The download address of the data manual is: https://download.csdn.net/download/qq_33231534/12501985
2. Introduction to EEPROM (AT24C64)
1. EEPROM bus timing
AT24C32/64 provides 32,768/65,536-bit serial electrically erasable and programmable read-only memory (EEPROM), organized into 4096/8192 words of 8 bits each. The cascading feature of this device allows up to 8 devices to share a common 2-wire bus. The device is optimized for many industrial and commercial applications, where low power and low voltage operation is essential. The chip pin diagram is as follows:
The hardware functions are as follows:
| Pin | Description |
| SCL | Serial clock input, the SCL input is used to clock data into each EEPROM device on the rising edge, and clock data out of each device on the falling edge. |
| SDA | For the serial data line, the SDA pin is a two-way serial data transmission. This pin is open-drain driven and can be connected to any number of other open-drain or open-collector devices. |
| A2, A1, A0 | Device address input. When these pins are hardwired, up to 8 32K/64K devices can be addressed on a single bus system. When the pins are not hardwired, the default A2, A1 and A0 are zero. |
| WP | Write protection, when connected to GND, the write protection input allows normal write operations; when WP is connected to VCC, all upper part of the memory (8/16K) write operations are restricted; if not connected, WP is internally pulled down To GND. |
The bus timing is as follows:
The write cycle sequence is shown in the figure below: The write cycle time is the time from the effective stop of the write sequence to the end of the internal clear/write cycle.
Compared with the timing situation of the above two figures, the AC characteristic table is as follows:
Some basic operations of the device are as follows:
- Clock and data conversion: SDA pin is usually pulled high with external devices. The data on the SDA pin can only be changed during SCL low time (refer to the data validity timing diagram). SDA data changes during SCL peak periods will indicate start or stop conditions as defined below.
- Start condition: When SCL is high, SDA has a falling edge.
- Stop condition: When SCL is high, SDA has a rising edge. After reading a sequence, the stop command places the EEPROM in standby power mode.
- Acknowledgement (ACK): All addresses and data words are serially transmitted or received from EEPROM in 8-bit words. The EEPROM sends a 0 (low level) in the 9th clock cycle to confirm that it has received each word.
- Standby mode: AT24C32/64 is a low-power standby mode, the on state is: a) after power-on; b) after receiving the stop bit and completing internal operations.
The data valid bits, start and stop conditions, and output response in the above figure are the same as the I2C protocol mentioned above, so I won't go into too much detail here.
2. EEPROM read and write timing
2.1 Device address
32K/64K EEPROM requires an 8-bit device address word to enable the chip to perform read or write operations under startup conditions. The device address word consists of a forced sequence of the first four bits 1, 0, as shown in the figure. This is common to all 2-wire EEPROM devices. 32K/64KEEPROM uses three device address bits A2, A1, A0, allowing up to 8 devices on the same bus. These bits can be set via hardwired input pins. The A2, A1, and A0 pins use internal dedicated circuits. If the pins are allowed to float, they will be biased to a logic low level.
The eighth bit of the device address is the read/write operation selection bit. If this bit is high, a read operation is initiated; if this bit is low, a write operation is initiated. When the EEPROM compares the address sent by the master device, the EEPROM will output a 0. If it is not the same, the device will return to standby.
2.2 Write operation
2.2.1 Byte write
The write operation requires two 8-bit data word addresses after the device address word and response (ACK). After receiving the first data word address, the EEPROM will respond with a 0 again. After receiving the second data word address, the EEPROM responds with a 0 again. Then transfer the data to be written, and stop reading and writing after the EEPROM responds with a 0. At this time, the EEPROM enters the internal timing write cycle of the non-volatile memory . All inputs are disabled during this write cycle, and the EEPROM will not respond until the end of the write.
2.2.2 Page write
The 32K/64K EEPROM can perform 32-byte page write operations. The start method of the page write is the same as the byte write, but the microcontroller will not enter the stop condition after sending the first data word. Conversely, after the EEPROM confirms that it has received the first data word, the microcontroller can transmit up to 31 more data words. The EEPROM will respond with zero after receiving each data word. The microcontroller must use a stop condition to terminate the page write sequence (see the figure above).
The address of the data word below 5 bits (32) is incremented internally after each data word is received. Data word address bits higher than 5 bits are not incremented and the memory page row position is maintained. When the internally generated word address reaches the page boundary, the following byte is placed at the beginning of the same page. If more than 32 data words are transferred to the EEPROM, the data word address will "roll" and the previous data will be overwritten.
2.3 Read operation
Except that the read/write selection bit in the device address word is set to 1, the start mode of the read operation is the same as the write operation. There are three read operations: current address read, random address read and sequential read.
2.3.1 Current address read
The internal data word address counter holds the last address accessed during the last read or write operation, incrementing by 1. As long as the chip power remains the same, this address remains valid between operations. Address "rolling" during reading is from the last byte of the last memory page to the first byte of the first page. The address "rolling" during writing is from the last byte of the current page to the first byte of the same page.
2.3.2 Random address read
Random reads require a "pseudo" byte write sequence to load the data word address. Once the device address word and data word address are recorded and confirmed by the EEPROM, the microcontroller must generate another start condition, and then the microcontroller starts a current address read operation, sending a device address and read/write selection bit high. The EEPROM confirms the device address and continuously counts the output data words. The microcontroller does not respond to a zero, but generates a stop condition (see figure above).
2.3.3 Sequential Read
Sequential reading is started by current address reading or random address reading. After the microcontroller receives a data word, it responds with an ACK. As long as the EEPROM receives a response, it will continue to increment the data word address and serial clock output sequential data words. When the memory address limit is reached, the data word address will "roll" and sequential reading will continue. When the microcontroller does not respond with 0, but sends a stop condition, the sequential read operation is terminated.
The above explanation of the AT24C64 EEPROM is based on the AT24C32/AT24C64 chip data manual of ATMEL. Those who need to watch or download can go to the following website: https://pdf1.alldatasheet.com/datasheet-pdf/view/56068/ATMEL/ AT24C64.html