Table of contents

1. The basic concept of communication

1. Serial communication and parallel communication (according to the data transmission method)

Serial communication: refers to the communication method that transmits data one by one in the form of data bits through a small number of data signal lines (generally less than 8), ground wires and control signal lines.

Parallel communication: refers to the communication method that uses 8, 16, 32 and 64 or more data lines for transmission, and transmits data of multiple data bits at the same time.

Comparison of the two: when the data transmission rate is the same, the parallel efficiency is higher and more data can be transmitted; while the serial communication saves costs. Parallel transmission has high requirements for synchronization, and with the increase of communication rate, the problem of signal interference will significantly affect the communication performance. Compare as follows:

2. Full-duplex, half-duplex, simplex communication (according to data communication direction)

Full-duplex: At the same time, two devices can send and receive data at the same time;

Half-duplex: data can be sent and received between two devices, but not at the same time;

Simplex: Only one direction of communication can be carried out at any time, and one side is fixed as the sending device and the other as the receiving device.

3. Synchronous communication and asynchronous communication (synchronous mode of data communication): whether to use clock signal to distinguish

Synchronous communication: Both parties of the transceiver device will use a signal line to represent the clock signal, and the two parties will coordinate and synchronize data under the drive of the clock signal. In communication, both parties usually agree to sample the data line at the rising or falling edge of the clock signal.

Asynchronous communication: do not use the clock signal for data synchronization, directly intersperse some synchronization signal bits in the data signal, or pack the main data, and transmit the data in the format of data frame. In some communications, both parties need to agree on the transmission of data rate for better synchronization.

Comparison between the two: In synchronous communication, most of the content transmitted by the data signal is valid data, while in asynchronous communication, various identifiers of frames will be included, so the efficiency of synchronous communication is higher, but the clocks of both parties in synchronous communication The allowable error is small, but the allowable error of the clocks of both parties in asynchronous communication is relatively large.

4. Communication rate: bit rate and baud rate

Bit rate (Bitrate): The number of binary digits transmitted per second, in bits per second (bit/s).

Baudrate: Indicates how many symbols are transmitted per second.

2. USART——serial port communication

Including RS232, RS499, RS423, RS422 and RS485 interface specifications and standard specifications.

The physical layer and protocol layer of the serial port communication protocol:

1. Physical layer: There are many standards and variants for the physical layer of serial communication, the main one is RS-232 standard, generally only three signal lines RXD, TXD and GND are used to directly transmit data signals.

2. Protocol layer: The data packet of serial port communication is transmitted from the sending device to the RXD interface of the receiving device through its own TXD interface. In the protocol layer of serial port communication, the content of the data packet is stipulated, which is composed of start bit, main data, check bit and stop bit. The data packet format of the communication parties must be consistent to send and receive data normally.

Data validation:

Odd parity: The number of "1" in the valid data and parity bits is odd;

Even parity: the number of "1" in the valid data and parity bits is an even number;

3. USART - Universal Synchronous Asynchronous Receiver and Transmitter (Universal Synchronous Asynchronous Receiver and Transmitter)

RX、TX

Serial communication: Data is transmitted in frame format, that is, frame-by-frame transmission. Each frame contains start signal, data information, stop information, and possibly check information.

Character frame: A character frame transmission requires three parts: start bit + data frame + stop bit. The start bit is the low level of a bit period, and the bit period is the time occupied by each bit; the data frame is the 8-bit or 9-bit data we want to send, and the data is transmitted from the lowest bit; the stop bit is a certain time cycle high.

3. I2C communication protocol

I2C communication protocol (Inter-Integrated Circuit): developed by Philps, because it has few pins, simple hardware implementation, strong scalability, and does not require external transceiver devices such as USART, CAN and other communication protocols, it is now widely used in Communication between multiple integrated circuits (ICs) in a system.

1. Physical layer: bidirectional serial data line (SDA), serial clock line (SCL)

(1) It is a bus that supports devices. A "bus" refers to a signal line shared by multiple devices. In one I2C communication bus, multiple I2C communication devices can be connected to support multiple communication masters and multiple communication slaves.
(2) An I2C bus uses only two bus lines, a bidirectional serial data line (SDA) and a serial clock line (SCL). The data line is used to represent data, and the clock line is used to synchronize data transmission and reception.

(3) Each device connected to the bus has an independent address, and the host can use this address to access between different devices.
(4) The bus is connected to the power supply through a pull-up resistor. When the I2C device is idle, it will output a high-impedance state, and when all devices are idle, they will output a high-impedance state, and the pull-up resistor will pull the bus to a high level.
(5) When multiple hosts use the bus at the same time, in order to prevent data conflicts, arbitration will be used to determine which device occupies the bus.

2. Protocol layer: defines communication start and stop signals, data validity, response, arbitration, clock synchronization and address broadcasting.

(1) I2C basic reading and writing process

S: transmission start signal; SLAVE_ADDRESS: slave address; R/W: transmission direction selection bit, 1 for reading, 0 for writing
A/A: response (ACK) or non-response (NACK) signal; P: stop transmission signal

Communication process : After the start signal is generated, all slaves start to wait for the slave address signal (SLAVE_ADDRESS) broadcast by the master next. On the I2C bus, the address of each device is unique. When the address broadcast by the host is the same as that of a certain device, the device is selected, and the unselected devices will ignore subsequent data signals. According to the I2C protocol, this slave address can be 7 bits or 10 bits. After the address bit, it is the selection bit of the transmission direction. When this bit is 0, it means that the subsequent data transmission direction is from the master to the slave, that is, the master writes data to the slave. When this bit is 1, it is the opposite, that is, the master reads data from the slave. After the slave receives the matching address, the master or the slave will return an acknowledgment (ACK) or non-acknowledgement (NACK) signal, and the master can continue to send or receive data only after receiving the acknowledgment signal.

Reading and writing data: I2C communication is more commonly used in a composite format, and there are two start signals (S) in the transmission process. Generally, in the first transmission, after the host finds the slave device through SLAVE_ADDRESS, it sends a piece of "data", which is usually used to represent the internal register or memory address of the slave device (note the difference between it and SLAVE_ADDRESS); In the second transmission, the content of the address is read or written. The first communication is to tell the slave to read and write the address, and the second is the actual content of reading and writing.

(2) Communication start and stop signals: start and stop signals are generally generated by the host

Start signal: SCL is high, SDA is high—>low;

Stop signal: SCL is high, SDA is low -> high;

(3) Data validity: During transmission, when SCL is high level, the data indicated by SDA is valid, that is, when SDA is high level, it means data "1", and when it is low level, it means data "0". When SCL is low level, the data of SDA is invalid. Generally, at this time, SDA performs level switching to prepare for the next data representation.

3. I2C features and architecture

Software simulation protocol: directly control the two GPIO pins of the chip, which are used as SCL and SDA respectively. According to the timing requirements of the above signals, directly control the output of the pin (if receiving data, read the SDA level), it can be realized I2C communication. When the communication sequence is generated by directly controlling the level of the GPIO pin, the state of the pin at each moment needs to be controlled by the CPU.

Hardware protocol: The I2C on-chip peripheral of STM32 is responsible for implementing the I2C communication protocol. As long as the peripheral is configured, it will automatically generate communication signals according to the protocol requirements, send and receive data and cache them. The CPU only needs to detect the status and access of the peripheral. The data register can complete the data sending and receiving.

4. SPI communication protocol

SPI (Serial Peripheral Interface): Serial Peripheral Interface, is a high-speed full-duplex communication bus.

1. SPI physical layer: 3 buses and chip selection lines (SCK, MOSI, MISO, and chip selection lines total 4)

(1) Chip selection line: Slave device selection signal line. When there are multiple SPI slave devices connected to the SPI master, the other signal lines SCK, MOSI and MISO of the device are connected to the same SPI bus in parallel at the same time, that is, no matter how many The slave devices all use these 3 buses in common; and each slave device has an independent NSS signal line. This signal line exclusively occupies a pin of the host, that is, there are as many slave devices as there are chip selects. signal line. In the I2C protocol, the device address is used to address, select a device on the bus and communicate with it; while there is no device address in the SPI protocol, it uses the NSS signal line to address. When the host wants to select a slave device, the slave When the NSS signal line of the device is set to low level, the slave device is selected and the chip selection is valid, and then the host starts SPI communication with the selected slave device. Therefore, the SPI communication starts with the NSS line being set low, and the end signal is when the NSS line is pulled high.

(3) MOSI (Master Output, Slave Input): Master output/slave input pin. The data of the master is output from this signal line, and the slave reads the data sent by the master through this signal line, that is, the direction of the data on this line is from the master to the slave.
(4) MISO (Master Input, Slave Output): Master device input/slave device output pin. The host reads data from this signal line, and the data from the slave is output to the host through this signal line, that is, the direction of data on this line is from the slave to the host.

2. Protocol layer: The SPI protocol defines the communication start and stop signals, data validity, clock synchronization and other links.

SPI communication timing:

(1) Communication start and stop signals:

Start signal: NSS signal line changes from high to low, which is the start signal of SPI communication. NSS is the exclusive signal line of each slave. When the slave detects the start signal on its own NSS line, it knows that it has been selected by the master and starts to communicate with the master.

Stop signal: The NSS signal changes from low to high, which is the stop signal of SPI communication, indicating that the communication is over and the selected state of the slave is cancelled.

(2) Data validity: SPI uses MOSI and MISO signal lines to transmit data, and SCK signal line for data synchronization. The MOSI and MISO data lines transmit one bit of data in each clock cycle of SCK, and the data input and output are performed simultaneously. The data of MOSI and MISO changes and outputs during the rising edge of SCK, and is sampled at the falling edge of SCK. That is, at the time of the falling edge of SCK, the data of MOSI and MISO are valid, when the level is high, it means data "1", when it is low level, it means data "0". At other times, the data is invalid, and MOSI and MISO prepare for the next representation of data. Each SPI data transmission can be in 8-bit or 16-bit units, and the number of units per transmission is not limited.

Five, DMA - direct memory access

DMA (Direct Memory Access): It is a peripheral of the single-chip microcomputer. Its main function is to move data, but it does not need to occupy the CPU. That is, when transferring data, the CPU can do other things, like multi-threading. Data transfer support from peripheral to memory or memory to memory

1. DMA request: If the peripheral device wants to transmit data through DMA, it must first send a DMA request to the DMA controller. After the DMA receives the request signal, the controller will send a response signal to the peripheral device. When the peripheral device responds and the DMA After the controller receives the response signal, it will start the DMA transmission until the transmission is completed.

2. Channels: DMA has 12 independently programmable channels, DMA1 has 7 channels, DMA2 has 5 channels, and each channel corresponds to DMA requests from different peripherals. Although each channel can receive multiple peripheral requests, it
can only receive one request at a time, and cannot receive multiple requests at the same time.

3. Arbiter: When multiple DMA channel requests occur, it means that there is a problem of the order of response processing, which is handled by the arbiter.

4. DMA data configuration: DMA transfers data in three directions—from peripheral to memory, from memory to peripheral, and from memory to memory.

6. Comparison of USART/I2C/SPI

1. Communication rate comparison:

SPI > I2C > UART
(1) Synchronous communication > Asynchronous communication;
(2) There must be a clock line connecting the two ends of the transmission during synchronous communication;
(3) Both are serial communication methods, and parallel communication is used for communication between internal storage , such as flash;
(4) The distance suitable for transmission is inversely proportional to the communication rate;

2. Connection mode:
SPI: 2 data lines, 1 clock line, 1CS (equipment chip select line), serial synchronous communication full duplex;
I2C: 1 data line, 1 clock line, serial synchronous communication half duplex, The transmission distance is shorter than UART;
UART: 2 data lines, 1 ground line, serial asynchronous communication full duplex, the transmission distance is longer than I2C;

(I2C interface is an "inter-device" interface, which transmits data within a board)
(UART is an "inter-device" interface, which is more used to transmit data between two devices)

Communication protocols in embedded - UART, I2C, SPI, DMA