Protocol analysis of I2C interface controller

The I2C bus uses a multi-master-slave architecture, which is generally used in situations with small data volumes and short transmission distances.

I2C protocol analysis

The interface requires a total of two bus lines, namely SCL (serial clock line) and SDA (serial data line). The I2C bus is half-duplex, so there can only be one host at any time, and each I2C device has one Unique device address. Bidirectional data transmission is carried out between the master device and the slave device on the bus in units of bytes.

I2C protocol regulations

1. The data bus (SDA) must remain stable when SCL is high, so the data bus (SDA) can only change when it is low. As shown below
   

2. When the clock is high, the jump of the data bus from high to low becomes the start signal of the bus, and the jump of the data bus from low to high becomes the stop signal of the bus.
   

3. Response, when the I2C master transmits 8-bit data or command, it will release the data bus (SDA), that is, set it to the input state, and then wait for the slave to respond. If the response signal is low level 0, it means response, and high power Level 1 means non-response, but the clock at this time is still provided by the host.
   
   The format of the data frame. During I2C communication, the "start signal" is first sent, followed by the seven-bit period address. The eighth bit is the data transfer direction bit, where 0 represents writing, 1 represents reading, and the following is Wait for the slave's response. After the entire transmission is over, the termination signal is generated by the host. In addition, it should be noted that when sending data, the high bit is sent first.

I2C device address

Each I2C device has a device address. Some device addresses are set at the factory and cannot be changed by the user (for example, the OV7670 device address is fixed 0x42). Some have a certain number of addresses, and the remaining few are determined by Determined by hardware (for example, the EEPROM memory of the common I2C interface has 3 pins for controlling the address, which are determined by the user during hardware design).
Strictly speaking, the master does not directly send the address to the slave, but the master sends the address to the bus. All slaves can receive the address sent by the master, and then each slave compares the address sent by the master with its own address. , if matched, the slave will send a response signal to the bus. After the master receives the response signal, it starts to send data to the bus, and the communication with the slave is established. If the host does not receive a response signal, it means addressing failed.
When the I2C protocol transmits data, the host needs to first send a control command to the bus. The control command includes the slave device address and read and write control, and then waits for the slave to respond. The data format for control command transmission is as follows:

During I2C transmission, transmission is carried out in order from high to low. The lowest bit of the control byte is the read and write control bit. When it is 0, it means that the master is writing to the slave. When this bit When it is 1, it means that the master reads from the slave.

I2C memory address

Every device that supports the I2C protocol always has some internal registers or memories that can be read and written. For example, the EEPROM memory is a series of sequentially addressed storage units; the CMOS camera model OV7670 (the interface of OV7670 is called The SCCB interface is essentially a special I2C protocol and can be directly compatible with the I2C protocol). Inside it is a series of addressable registers that can be read and written. Therefore, if we want to read and write the storage unit (register and memory, hereinafter referred to as the storage unit) in a device, we must be able to specify the address of the storage unit.

I2C write timing

The process of writing single-byte data from a single-byte address:
1. The host sets SDA as output;
2. The host sends a start signal;
3. The host transmits the device address byte, of which the lowest bit is 0, indicating a write operation;
4. The host sets SDA It is a tri-state gate input to read the response signal from the slave;
5. If the response signal is read successfully, the master sets SDA as an output and transmits 1-byte address data.
6. The host sets SDA as a three-state gate input and reads the slave response signal;
7. After reading the response signal successfully, the host sets SDA as an output and transmits the data to be written;
8. The host sets SDA as a three-state gate input, Read the response signal from the slave;
9. If the response signal is read successfully, the master generates a STOP bit to terminate the transmission.

Continuous write timing:
Continuous writing (also called page writing, please note that I2C continuous writing timing is only supported by some devices) means that the host continuously writes multiple bytes of data to the slave. This is similar to a single-byte write operation, with multiple bytes in a row. The write operation is also divided into 1-byte address segment device and 2-byte address segment device write operation.

I2C read timing

The process of reading single-byte data from a single-byte address:
1. The host sets SDA as output;
2. The host initiates a start signal;
3. The host transmits the device address byte, of which the lowest bit is 0, indicating a write operation;
4. The host sets SDA as a three-state gate input and reads the slave response signal;
5. The response signal is read successfully, the host sets SDA as an output and transmits one byte of address data;
6. The host sets SDA as a three-state gate input and reads The slave responds to the signal;
7. The response signal is read successfully, and the host initiates the start signal;
8. The host transmits the device address byte, of which the lowest bit is 1, indicating a read operation;
9. Set SDA as a three-state gate input, and read The slave responds to the signal;
10. The response signal is read successfully. The host sets SDA as a three-state gate input and reads one byte of data on the SDA bus. 11. Generates a
no-response signal, that is, high level (no need to set it to output high level, because the bus will be automatically pulled high);
11. The host generates a stop bit to terminate the transmission;

continuous read timing
. Continuous reading means that the host continuously reads multiple bytes of data from the slave. This is similar to a single-byte read operation. Sequential multi-byte read operations are also divided into read operations for 1-byte address segment devices and 2-byte address segment devices.