In the future, GPT counters need to be used to implement interrupts and delays. Here we need to understand the functions of GPT and related registers.
Table of contents
3. Output comparison (two working modes of GPT)
1. Function of GPT timer
The gpt timer mainly includes the following three functions:
- counter
- Input capture (capture interrupt can be generated)
- Output compare (can generate compare interrupt) - note the mode of GPT
1. Counter
According to the route in the figure, you can roughly understand the order of configuration counters:
- The first step is to select the clock source, here we are still ipg_clk (66MHz)
- The second step is to select the frequency division number (1~4096)
Because the counter counts up, that is, it will increase by 1 every time a clock cycle passes.
2. Input capture
Input capture (Input Capture, ICR) can capture the rising or falling edge generated by the clock source and generate an interrupt. The GPT timer has two input capture channels
3. Output comparison (two working modes of GPT)
Output Compare (OCR) contains three output channels GPT_COMPARE1~3, the use of channels and the mechanism of triggering interrupts depend on the working mode of GPT:
- Restart Mode: Output Regx needs to be preset, when the value of the counter == Output Regx, a comparison interrupt will be generated (only applicable to GPT_COMPARE1)
- Free-Run Mode: The counter starts incrementing from 0, overflows after incrementing to 0xFFFFFFFF, and starts counting from 0 again
2. Register analysis
1、GPTx_CR
The GPT control register can control the clock source, input channel enable, output channel enable, etc. The following mainly analyzes some bits that need to be used later.
bit 0: GPT enable (start/disable GPT timer), generally wait until other registers are configured before setting this field.
bit 1: Set the initial value when the timer starts. 0 means to start counting from the value of the counter when it was closed last time, and 1 means to start counting from 0 again.
bit 8-6: Select clock source. We choose ipg_clk(66MHz)
bit 9: Select the working mode of GPT. Generally choose Restart Mode. (already introduced above)
bit 15: Set software reset state.
- After being set to the reset state, this bit will always be set to 1 as long as it is still in reset. Except for bit 0, 1, 2, 3, 5, other bits will be reset to default values.
- After the reset is completed, it will be automatically cleared, that is, set to 0
Replenish:
- IM1~2 sets the capture state, that is, rising edge or falling edge capture
- OM1~3 set the output state, that is, no output, output inversion, etc.
寄存器: GPT1_CR
基地址: 0x2098000
初始化操作:
// 禁用GPT定时器
GPT1_CR &= ~(1 << 0);
// 复位
GPT1_CR |= (1 << 15);
while((GPT1_CR >> 15) & 0x1); // 等待复位结束
/*
* 配置GPT定时器
* bit 1: 1
* bit 8-6: 001
* bit 9: 0
*/
GPT1_CR |= (1 << 1);
GPT1_CR &= ~((7 << 6) | (1 << 9));
GPT1_CR |= (1 << 6);
// ... 其他初始化操作
// 启动定时器
GPT1_CR |= (1 << 0);2、GPTx_PR
GPT frequency divider, you can set the frequency division number of the clock source. Bit 11-0 sets the frequency division number (1~4096)
寄存器: GPT1_PR
基地址: 0x2098004
初始化操作:
// 66 分频
GPT1_PR &= ~(0xFFF << 0); // 低 12 bit 清零
GPT1_PR |= (66 << 0); // 66 分频3、GPTx_SR
The GPT status register is a readable register and does not need to be set. Mainly save the following contents:
- Output comparison interrupt trigger status OF1~3
- Input captured interrupt trigger status IF1~2
- Overflow status (that is, whether the value of the counter is equal to the value of the comparator or whether it counts to 0xFFFFFFFF)
寄存器: GPT1_SR
基地址: 0x20980084、GPTx_IR
The GPT interrupt register mainly controls the interrupt enable of the input/output channel. The working mode of GPT above has been set to Restart Mode, so we need to enable output comparison channel 1.
寄存器: GPT1_IR
基地址: 0x209800C
初始化操作:
GPT1_IR |= (1 << 0); // 输出比较通道1 使能5、GPTx_OCRn
GPT outputs the comparison register, which saves the comparison value. In Restart mode, when the counter value == the comparison value, an interrupt is triggered. Suppose the delay is 10 ms, the clock source is 66 MHz, and the frequency division number is 66.
From this, we can know that the clock cycle is 1/1M, and the comparison value corresponding to a delay of 10ms = 1M * 0.01 = 10000
寄存器: GPT1_OCR1
基地址: 0x2098010
初始化操作:
GPT1_OCR1 |= (10000 << 0); // 设置通道1 的比较值为100006、GPTx_ICRn
The GPT input capture register holds the value of the counter when the capture interrupt is triggered.
寄存器: GPT1_ICR1
基地址: 0x209801C7、GPTx_CNT
The GPT count register saves the value of the counter at the current moment.
寄存器: GPT1_CNT
基地址: 0x2098024