The previous article introduced the source of the system clock, the clock tree, and the configuration steps of the PLL1 branch. We noticed that PLL2 and PLL3 have fixed frequency multipliers and cannot be modified, but the PFDx branches they divide can be modified . It's just that when we initialize, we still initialize according to the official frequency.
Table of contents
1. Understand the relevant registers
1. Understand the relevant registers
Now I only know the frequencies of PLL2_PFDx and PLL3_PFDx to be set, but I don't know which register to set them through. We can find the register corresponding to the PFD clock branch configuration under Functional Description in Chapter 18.
When the PLL changes from power-off to power-on loading or is in the re-locked state due to modification, it is required that the PFDx_CLKGATE bit of the CCM_ANALOG_PFD_480n or CCM_ANALOG_PFD_528n register changes from 1 to 0 after the PLL is locked.
This is the first sentence below. The information we can get from this sentence is:
- Modify PLL2_PFDx : Need to operate CCM_ANALOG_PFD_528n register
- Modify PLL3_PFDx : Need to operate CCM_ANALOG_PFD_480n register
- Common point : they all need to operate the PFDx_CLKGATE bit and set it to 0
2. PLL2_PFDx initialization
PLL2_PFDx is controlled by CCM_ANALOG_PFD_528 register. We will find that PFD0~3, each PFDx has a set of fields, taking PFD0 as an example:
- PFD0_FRAC: The frequency division number of PLL2_PFD0. The calculation formula is as follows, where the value range of PFD0_FRAC is 12~35. Assume that we set the PLL2_PFD0 value to 352 according to the official value , then PFD0_FRAC should be equal to 27, that is, the PFD0_FRAC field should be set to 0x1b
PLL2_PFD0 = 528 × 18 / PFD0_FRAC
- PFD0_STABLE: This field is read-only and is only used to determine whether PLL2_PFD0 is stable.
- PFD0_CLKGATE：
- Set to 1, the frequency divider is disabled, that is, the PLL2_PFD0 output is turned off;
- Set to 0, the frequency divider is enabled, that is, the PLL2_PFD0 output is enabled
PLL2 has four channels in total, so we need to calculate the frequency division number of each channel in turn.
寄存器: CCM_ANALOG_PFD_528
基地址: 0x20C8100
初始化操作:
unsigned int reg = 0;
reg |= (27 << 0); // PFD0 分频数(27)
reg &= ~(1 << 7); // 分频使能
reg |= (16 << 8); // PFD1 分频数(16)
reg &= ~(1 << 15); // 分频使能
reg |= (23 << 16); // PFD2 分频数(23)
reg &= ~(1 << 23); // 分频使能
reg |= (47 << 24); // PFD3 分频数(47)
reg &= ~(1 << 31); // 分频使能
CCM_ANALOG_PFD_528 = reg;
3. PLL3_PFDx initialization
The initialization process of PLL3_PFDx is the same as that of PLL2_PFDx, which is controlled by the CCM_ANALOG_PFD_480 register. The difference lies in the formula for calculating the frequency division number.
- PFD0_FRAC: Frequency division number of PLL3_PFD0
PLL2_PFD0 = 480 × 18 / PFD0_FRAC
- PFD0_STABLE: This field is read-only and is only used to determine whether PLL3_PFD0 is stable.
- PFD0_CLKGATE：
- Set to 1, the frequency divider is disabled, that is, the PLL2_PFD0 output is turned off;
- Set to 0, the frequency divider is enabled, that is, the PLL2_PFD0 output is enabled
寄存器: CCM_ANALOG_PFD_480
基地址: 0x20C80F0
初始化操作:
unsigned int reg = 0;
reg |= (12 << 0); // PFD0 分频数(12)
reg &= ~(1 << 7); // 分频使能
reg |= (16 << 8); // PFD1 分频数(16)
reg &= ~(1 << 15); // 分频使能
reg |= (17 << 16); // PFD2 分频数(17)
reg &= ~(1 << 23); // 分频使能
reg |= (18 << 24); // PFD3 分频数(18)
reg &= ~(1 << 31); // 分频使能
CCM_ANALOG_PFD_480 = reg;