UART / USRAT, I2C, SPI communication literacy

EDITORIAL:
This article aims to summarize the backup, to facilitate future inquiries, as is the personal summary, if wrong, please correct me; in addition, most of the content from the Internet, books, and various manuals, should please inform the infringement, immediately delete posts to apologize.

一、UART/ USRAT

Basic Concepts serial UART / USRAT communications

1.1 Basic manner
substantially parallel mode communication and serial communication points

1.1.1 Parallel Communication
parallel communication means simultaneously each transmit or receive a plurality of data lines in the data.

Characterized by simultaneous transmission of each data bit, high speed, high efficiency, there are data bits required number of data lines, a high transmission cost. Inside the integrated circuit chip, data transfer between the respective members and the like using the same hardware board parallel fashion from the parallel communications transmission is generally less than 30m.

1.1.2 Serial Communications
Serial communication means in the event of one or each of the received data the same data line bit by bit in the order.

Characterized by a data bit sequence, a minimum time to complete a transmission line, low cost, slow. A computer and a remote terminal, the remote terminal the data transmission between the same are often serial.

1.1.3 Comparison serial communication and parallel communication
salient features of serial communication: long distance transmission, from a few meters to several kilometers, the clock frequency of the serial communications easier to improve communication, anti-jamming, between its signal mutual interference can be completely ignored, but serial communication is much slower than parallel communication. Serial communication has been widely used in data acquisition and control system.

1.2 operating mode
based single-wire serial communication is transmitted, data is typically transmitted between the two sites, divided into three transmission modes in accordance with the direction of data flow:

1.2.1 simplex mode (Simplex)
data in simplex mode is unidirectional, communication is both one of the transmitting side, the other side is fixed to the receiver. Transmitting information in one direction only, using a data cable.
Such as a radio, can receive transmission data column to it, does not give tower retransmission data.

1.2.2 Half-duplex mode (Half duplex)
half-duplex communication mode refers to both parties transmitter and receiver, the two sides can transmit both can receive, but can not receive and transmit at the same time.

Generally half-duplex data transmission in both directions of the case, for example, intercom.

1.2.3 full duplex mode (Full duplex)
duplex data communication data are transmitted from the two transmission lines may transmit and receive simultaneously at two different sites, communications can both transmit and receive operations at the same time.

Full-duplex mode, each end of the transmitter and the receiver, there are two transmission lines may be used in an interactive application, the high efficiency of information transmission, such as mobile phones.

1.3 synchronized manner
according to the data synchronization method of communication, can be divided into synchronous and asynchronous, whether to use a clock signal to be differentiated according to the process of communication.

• In synchronous communications, the transceiver uses the above signal line for transmitting a signal, coordination, synchronization data in both the driving clock signal. For example, communication will typically both be predetermined uniform sampling of the data lines in the rising or falling edge of the clock signal.
  
• Not used in the asynchronous communication data synchronization clock signals, some signals are interspersed with synchronization bits in a data signal directly, or the data relating to the package, the transmission data frame format data. Communication also requires both sides of the Statute transmission rate of good data, etc., in order to better synchronize.

In synchronous communications, a majority of the contents of the transmitted data signal is valid data, and asynchronous communication will be various data frame will contain the identifier, the synchronization communication efficiency is high, but both the clock synchronous communication allows a small error, a little clock error could cause data disorder, asynchronous communication allows both the clock error is larger.

Two, I2C

2. I2C basic concepts

I2C总线是 PHLIPS公司在 20世纪 80年代推出的一种串行总线。具有引脚少，硬件实现简单，可扩展性强的优点。I2C总线的另一优点是支持多主控，总线上任何能够进行发送/接收数据的设备都可以占领总线。当然，任意时间点上只能存在一个主控。

I2C即是一种总线，也是一种通讯协议。在嵌入式开发中，通讯协议可分为两层：物理层和协议层。物理层是数据在物理媒介传输的保障；协议层主要是规定通讯逻辑，同一收发双方的数据打包、解包标准。打个比方，物理层相当于现实中的公路，而协议层则是交通规则，汽车可以在路上行驶，但是需要交通规则对行驶规则进行约束，不然将出现危险，也就是数据传输紊乱、丢包。

特性：

• 2条双向串行线，一条数据线 SDA，一条时钟线 SCL。
  SDA传输数据是大端传输，每次传输 8bit，即一字节。
• 支持多主控(multimastering)，任何时间点只能有一个主控。
• 总线上每个设备都有自己的一个 addr，共 7个 bit，广播地址全0.
• 系统中可能有多个同种芯片，为此 addr分为固定部分和可编程部份，细节视芯片而定，看 datasheet

2.1. 物理层
I2C通讯系统接线图如下：

(1) 在I2C通讯总线上，可连接多个 I2C通讯设备，支持多个通讯主机和多个通讯从机
(2) I2C通讯只需要两条双向总线：串行数据线 (SDA)，串行时钟线 (SCL)。数据线用于传输数据，时钟线用于同步数据收发
(3) 每个连接到总线的设备都有一个独立的地址，主机正是利用该地址对设备进行访问
(4) SDA和 SCL总线都需要接上上拉电阻，当总线空闲时，两根线均为高电平。连接到总线上的任意器件输出低电平都会将总线信号拉低。即各器件的 SDA和 SCL都是线与的关系
(5) 多个主机同时使用总线时，需要用仲裁方式决定哪个设备占用总线，不然数据将会产生冲突
(6) 串行的8位双向数据传输位速率在标准模式下可达 100kbps，快速模式下可达 400kbps，高速模式下可达 3.4Mbps(目前大多数 I2C设备还不支持高速)

2.2. 协议层
协议层规约了通讯的起始、停止信号，数据有效性、响应、冲裁同步、地址广播等。

2.3. I2C位传输
数据传输：SCL为高电平时，SDA线若保持稳定，那么 SDA上是在传输数据bit；
数据改变：SCL为低电平时，SDA线才能改变传输的bit；
若 SDA发生跳变，则用来表示一个会话的开始或结束（后面讲）

2.3.1 I2C开始和结束信号
开始信号：SCL为高电平时，SDA由高电平向低电平跳变，开始传送数据。
结束信号：SCL为高电平时，SDA由低电平向高电平跳变，结束传送数据。

2.3.2 I2C应答信号
Master每发送完 8bit数据后等待 Slave的ACK。
即在第9个clock，若从 IC发 ACK，SDA会被拉低。
若没有 ACK，SDA会被置高，这会引起 Master发生 RESTART或 STOP流程，如下所示：

2.4 I2C写流程
写寄存器的标准流程为：

1. Master发起 START
2. Master发送 I2C addr（7bit）和w操作0（1bit），等待 ACK
3. Slave发送 ACK
4. Master发送 reg addr（8bit），等待ACK
5. Slave发送 ACK
6. Master发送 data（8bit），即要写入寄存器中的数据，等待 ACK
7. Slave发送 ACK
8. 第 6步和第 7步可以重复多次，即顺序写多个寄存器
9. Master发起 STOP

写一个寄存器

写多个寄存器

2.5 I2C读流程
读寄存器的标准流程为：

1. Master发送 I2Caddr（7bit）和 W操作1（1bit），等待 ACK
2. Slave发送 ACK
3. Master发送 reg addr（8bit），等待ACK
4. Slave发送 ACK
5. Master发起 START
6. Master发送 I2C addr（7bit）和 R操作1（1bit），等待 ACK
7. Slave发送 ACK
8. Slave发送 data（8bit），即寄存器里的值
9. Master发送 ACK
10. 第 8步和第 9步可以重复多次，即顺序读多个寄存器

读一个寄存器

读多个寄存器

三、SPI

3. SPI基本概念

SPI（serial peripheral interface，串行外围设备接口）总线技术是 Motorola公司推出的一种同步串行接口。它用于CPU与各种外围器件进行全双工、同步串行通讯。它只需四条线就可以完成MCU与各种外围器件的通讯，这四条线是：串行时钟线（CSK）、主机输入/从机输出数据线（MISO）、主机输出/从机输入数据线（MOSI）、低电平有效从机选择线 CS。

当 SPI工作时，在移位寄存器中的数据逐位从输出引脚（MOSI）输出（高位在前），同时从输入引脚（MISO）接收的数据逐位移到移位寄存器（高位在前）。发送一个字节后，从另一个外围器件接收的字节数据进入移位寄存器中。即完成一个字节数据传输的实质是两个器件寄存器内容的交换。主 SPI的时钟信号（SCK）使传输同步。其典型系统框图如下图所示。

3.1 通信原理
标准的 SPI 是 4 根线，分别是 SSEL（ 片选，也写作 SCS）、 SCLK（ 时钟，也写作 SCK）、 MOSI（ 主机输出从机输入 Master Output/Slave Input） 和 MISO（ 主机输入从机输出 Master Input/Slave Output）。

• MOSI(SDO)：主器件数据输出，从器件数据输入。
• MISO(SDI)：主器件数据输入，从器件数据输出。
• SCLK ：时钟信号，由主器件产生。
• CS：从器件使能信号，由主器件控制。(CS控制芯片是否被选中，只有片选信号为实现约定的使能信号时（高电位或地电位），对此芯片的操作才有效，这也就允许同一总线上连接多个SPI设备。)

SPI串行传输，数据一位一位从 MSB或 LSB开始传输，产生相应的脉冲沿时，MOSI，MISO才进行数据传输。

3.2 SPI总线工作方式
SPI有四种工作模式，取决于两个参数：（这两个参数其实就是控制了CLK这一根线，SPI通信不像UART或IIC那样有专门的通信周期，有专门的通信起始信号和结束信号。所以SPI协议能够通过控制时钟信号线在没有数据交流的时候保持的状态，要么是高电平，要么是低电平）

1、 CPOL，clock polarity，译作时钟极性。
2、 CPHA，clock phase，译作时钟相位。

• DETAILED DESCRIPTION CPOL:
  CPOL is used to define the clock signal is high or low in the idle state, on behalf of a high level 0 is low.
• DETAILED DESCRIPTION CPHA:
  First, in the synchronous interface, the interface must exist a clock used to synchronize the data sampling interface. CPHA is used to define the data sampled at several edge, the data sampling time. 1 represents the sampled second edge, is 0 for the first sample edge.

More than two parameters, a total of four combinations:
(. 1) the CPOL = 0, CPHA = 0: At this time, when the idle state, SCLK is low, the data is sampled at a first edge, i.e. by the SCLKLow to highHopping, the data is sampled on the rising edge, the data is transmitted on the falling edge.

(2) CPOL = 0, CPHA = 1: At this time the idle state, SCLK is at a low level, data is transmitted in the second edge, i.e. by the SCLKHigh to lowHopping, the data is sampled on the falling edge, data is transmitted at the rising edge.

(3) CPOL = 1, CPHA = 0: At this time the idle state, SCLK is high, the data is collected in a first edge, i.e. by the SCLKHigh to lowHopping, the data acquisition is the falling edge, data is transmitted at the rising edge.

(4) CPOL = 1, CPHA = 1: idle state at this time, SCLK is high, the data is transmitted at the second edge, i.e. by the SCLKLow to highHopping, the data acquisition is the rising edge, the data is transmitted on the falling edge.

Since there is no unified standard SPI, so the description of timing there are some differences, in particular datasheet prevail.