Quickly understand the i2c communication protocol
what is I2C?
Simply, it is the transmission data for two lines: a data line (SDA) a clock line (SCL).
I2C how transfer?
- The basic process
(1) the host sends a start signal;
(2) The host then issues a slave address byte information, wherein the lowest bit control code reader (1 to read, write 0), seven high a slave device. address;
(3) acknowledgment signal sent from the machine;
(4) the master starts the transmission signal, after each finished send a byte acknowledgment signal sent from the host machine;
(5) master issues a stop signal. - Signal specifically described above:
(1) start signal: during the clock line is high, the data line from high to low, a start signal is generated;
(2) the stop signal: the clock is high during the lines, data line from low to high, will generate a stop signal;
(3) a response signal: the acknowledgment signal, the host write slave, each byte written, if the machine correctly the next clock cycle the data line low effective to tell the host operating. When reading from the master machine, the correct reading one byte, the next clock cycle master should be the same data line low, acknowledgment signal sent telling machine has issued from the receipt of data (note: when the machine is read from the host last byte is received, it does not send an acknowledgment, a stop signal sent directly);
NOTE: any level change of the clock line is high-level period of the data lines are considered to be the start and stop signals, it is necessary to change the data changes when the clock is low. - Data format:
the I2C supports two data formats:
(. 1) 7bit / 10bit format address data;
(2) Format 7bit / 10bit addressing and repeat start signal. - From the device address:
Each device has its own addr on a bus, a total of 7 bit, broadcast address all zeros.
The system may have multiple isoforms chips, for addr divided into a fixed part and a programmable part, depending on the details of the chip set, see datasheet. - Hardware configuration:
Each internal device bus I2C SDA, SCL pin is the same circuit configuration, the output pin and an input buffer driven together. Wherein the output is open-drain FET, an input buffer with high input impedance of the phase. This circuit has two characteristics:
(1) Since the SDA, SCL are open-drain, by means of an external pull-up resistor on the signal "line and the" logic;
(2) while the output signal of the pin will level on the pin for testing, test whether the output just the same. Provide hardware foundation for the "clock synchronization" and "bus arbitration."
I2C few questions
- Simulation I2C I2C hardware What is the difference
(1) Principle: I2C hardware (dedicated providing SDA, SCL port) produced by the system clock is typically generated by dividing the crystal. Simulation I2C programmed analog clock and data lines.
(2) Control: I2C hardware implement various operations through a hardware interrupt. I2C analog concept without interruption, the level of the set through the IO port set low to achieve high writing and reading.
(3) Performance: the hardware more efficient and stable mode. - MPU6050 and MPU9250 I2C-
before for the two chips through the I2C address bit messy operation, such as to obtain the original values of the accelerometer, first transmission start signal, then transmitting the slave address (I2C device address), then send address register (where many people will mess up, because you want to send the address twice, the first time is the I2C device address, the second is the accelerometer address), then in order to obtain the original data.
How to achieve I2C?
All bedding before is to realize I2C communication, so how implementation is also particularly critical of a problem with the code.
The following is a reading and writing process is the I2C:
- Write register standard process is:
(. 1) Master initiates the START
(2) Master transmits I2C addr (7bit) and w Operation 0 (1bit), waits for the ACK
(. 3) the Slave transmits the ACK
(. 4) Master transmits reg addr (8bit), waiting for the ACK
(. 5) the Slave transmits the ACK
(6) Master transmits data (8bit), i.e., data to be written in the register, waiting for the ACK
(7) the Slave transmits the ACK
(. 8) step 6 and step 7 can be repeated, i.e., sequential write multiple registers
(9) Master initiates STOP - Read register standard process is:
(. 1) Master transmits I2C addr (7bit) and w Operation 1 (1bit), waits for the ACK
(2) the Slave transmits the ACK
(. 3) Master transmits reg addr (8bit), waits for the ACK
(. 4) the Slave transmitting the ACK
(. 5) Master initiates the START
(. 6) Master transmits I2C addr (7bit) and r 1 (1bit) operation, waiting for the ACK
(. 7) the Slave transmits the ACK
(. 8) the Slave transmits data (8bit), i.e. register values
( 9) Master transmits the ACK
(10) step 8 and step 9 may be repeated a plurality of times, i.e., sequentially reading a plurality of registers
