1. Data preparation. For Silicon Ensemble CDN design in terms of the rear end of the data are required to be provided by the factory standard cell Foundry, macrocells and I / O Pad library file, a physical library comprising the LEF, LIBERTY timing library and library NETLIST netlist, are given in the form of .lef, .tlf and the .v. After the front end of the chip design integrated gate-level netlist generated NETLIST, SDC, and having a clock timing constraints defined script file and .gcf constraints resulting file and the definition of power Pad DEF (Design Exchange Format) file. (In terms of Astro synopsys, after generation of integrated gate-level netlist, SDC timing constraints file is the same as the standard unit definition file Pad --tdf, .tf file --technology file, Foundry plant to provide macro unit and I / O Pad library file is given (Milkway reference library and DB, LIB file) and FRAM, cELL view, LM view form
2. layout, mainly standard cell layout, I / O Pad and macrocells. I / O Pad positions given in advance, and the macro cell is performed in accordance with the timing requirements placed, given the standard cell is placed in a certain area automatically by the tool. after the layout plan, the size of the chip, Core area, Row form, the power supply and the ground are determined Ring Strip down and, if necessary, after the automatic placement of standard cells and macrocells, you can do first the PNA (Network power Analysis) -.. the IR drop and the EM
3. placement - Auto standard cell placement. after the layout planning, the position macrocell, I / O Pad and standard cell placement areas have been identified, the information SE (Silicon Ensemble) will be transferred to the PC (Physical Compiler) by DEF file, PC According to obtain netlist and timing constraints information given by the .DB comprehensive file for automatic standard cell placement, and timing checks and cell placement optimization. If you are using a PC + Astro
Then you available write_milkway, read_milkway transfer data.
4. When the clock tree to (CTS Clock tree synthesis). Chip clock network to drive all of the timing circuit means, the clock source gate tape carrier unit number, the load and delay great unbalance, and to reduce the load balancing buffer insertion delay. And a clock buffer on the network constituting the clock tree. Generally repeated several times before they can make an ideal clock tree. Clock skew ---.
5. After the STA static timing analysis and simulation. After the clock tree is inserted, determines the position of each unit down, the tool can be made in the form of Global Route parasitic connection, in which case the extraction of the delay parameters is more accurate. SE and .SDF the .V file is passed to make PrimeTime static timing analysis. After confirming that no timing violations, these two files to be passed to the front end staff to do the simulation. For Astro, after the detail routing, extracted with starRC XT parameters, the resulting file is passed to EV and .SDF do PrimeTime static timing analysis, it would be more accurate.
6. ECO (Engineering Change Order). For static timing analysis and the problems appearing in the simulation, circuit layout, and means of small modifications.
7. The insertion Filler (pad fliier, cell filler). Filler refers to a standard cell library and the I / O Pad library defined in independent logical filler, used to fill between the standard cells and standard cells, the gap between the I / O Pad and I / O Pad, primarily the diffusion layer is connected, to meet the design requirements and rules DRC.
8. wiring (Routing). Global route-- Track assign --Detail routing - Routing optimization process cabling is meant to meet the rules and restrictions of wiring layers, line width, line spacing and lower limits of each insulated electrical wire mesh reliable performance constraints conditions, depending on the circuit the connection relationship of each unit and the I / O Pad interconnection lines connected to them, which are carried out at the driving timing (timing driven) condition, to ensure that the wiring length on critical timing paths can be minimized. Clear Report --Timing
9. The Dummy Metal increases. Foundry plant has a predetermined density of the metal, so the metal density not less than a certain value, to prevent the etching stage in the chip manufacturing process of the metal layer is etched excessively connection decreases the performance of the circuit. Dummy Metal is added to increase the density of the metal.
10. DRC and LVS. DRC is a physical chip layout of graphics layers design rule checking (spacing, width), it also includes an antenna effect checks to ensure correct flow sheet. LVS is a main layout netlist and comparing circuit to ensure consistent flow sheet out of the circuit layout and the actual needs. .Astro also include LVS DRC and LVS checks --EDA tool Synopsy hercules / mentor calibre / CDN Dracula performed / Commands Check the DRC.
11. The Tape OUT. In all passes inspection and verification are correct in the case file to the final layout GDSⅡ Foundry plant for mask manufacturing.
https://www.cnblogs.com/zeushuang/archive/2012/08/09/2630375.html
