Foreword
Update idle.
According to reference, on the basis of Xilinx FPGA constraints organize, facilitate their future often read. Graphic part from references.
You can refer to the "Xilinx FPGA development of practical Tutorial 2nd Edition" 4.4 Constraints chapters.
You can refer to the "Xilinx FPGA authority Design Guide" section 2.7 and 6 chapters.
1, constraint files
Constraint file Xilinx ISE FPGA design there are three categories: user design files (.UCF), netlist constraint file (.ncf), physical constraints file (.PCF), timing constraints may be achieved, pin constraints, area constraints.
User written input in the design phase UCF files, NCF file and then generates a comprehensive design and UCF files generated PCF file finally been to achieve.
The highest priority UCF file.
2, UCF file syntax description
(1) grammar
UCF file syntax is as follows:
{NET|INST|PIN} "signal_name" Attribute;among them,
"Signal_name" refers to the name of the object bound, including the level where the object description;
"Attribute" to describe the specific constraints; statement must be a semicolon ";" end. Comments can be added with the "#" or "/ * * /."
Note that: UCF file is case sensitive, signal names must be the same case and design, but constraint keywords can be uppercase, lowercase, or even mixed case. E.g:
NET "CLK" LOC = P30; #作用：将CLK信号分配到FPGA的P30管脚上。"CLK" is the name of the signal constraint. LOC = P30, are bound by a particular meaning.
For all constraint files, using the same constraint keyword or reserved word signal design environment that name will generate an error message, unless it is in "" quotes, so when the input constraints file, preferably with "" All the signals name in quotes.
(2) wildcard
In the UCF file, wildcard refers to the "*" and "?." "*" Can represent any string and empty, "?" Represents a character. When editing constraint files, use wildcards can quickly select a set of signals, of course, these signals must be part of a total of strings that contain. E.g:
NET "*CLK?" FAST; #作用：将包含“CLK”字符并以一个字符结尾的所有信号，并提高了其速率。In the position constraint, the row and column numbers can be used in a wildcard. E.g:
INST "/CLK_logic/*" LOC = CLB_r*c7; #作用：把CLK_logic层次中所有的实例放在第7列的CLB中。(3) the definition of the design hierarchy
In the UCF file by wildcard * can specify the design level signal. The syntax rules are:
* 遍历所有层次
Level1/* 遍历level1及以下层次中的模块
Level1/*/ 遍历level1种的模块，但不遍历更低层的模块Example 4-5 According to the configuration shown in FIG. 4-75, each module using wildcards in Table 4-3 to traverse required.
3, pin and area constraints grammar
LOC FPGA design constraint is the most basic layout constraints and comprehensive constraint can be defined position of the base unit design in the FPGA chip, enabling absolute positioning, targeting and positioning range. Further, LOC also bound a set of basic units in a particular region. LOC statement can both write constraints file, can also be added directly to the design file. In other words, ISE of the underlying instrument editor FPGA (FPGA Editor), Floorplanner (Floorplanner) and the pin region and the main function of the constraints editor can be done by LOC the statement.
(1) LOC statement syntax
The basic LOC syntax is as follows:
INST "instance_name " LOC = location;Wherein "location" may be a legal or more positions of any of the FPGA chip. If a plurality of positioning required comma "," separated, as shown below:
LOC = location1,location2,...,locationx;Currently, it does not support multiple logical placed in the same location as well as multiple logical as to multiple locations. Incidentally, multiple location constraint is not designed to target all the positions, but in the layout process, in which a layout is randomly selected as the final layout position.
Range positioning syntax is:
INST “instance_name” LOC=location:location [SOFT];LOC the statement commonly positioned Table 4-4.
When using the completion port LOC definition syntax is as follows:
NET "Top_Module_PORT" LOC = "Chip_Port";Wherein, "Top_Module_PORT" signal for the user interface design top module, "Chip_Port" is the name of the pin of the FPGA chip.
LOC statement that there is a priority, when specifying LOC port and its port connection, priority wire the constraint is the highest. For example, in FIGS. 4-76, the priority is higher than the LOC = 11 LOC = 38.
(2) LOC Property Description
LOC constraint statement can position the pin by loading different properties, CLB, Slice, TBUF, block RAM, hard multipliers, global clock, digital phase locked loop (DLL), and DCM module resources, covering all the FPGA chip type of resource. Thus, very powerful statement LOC, LOC Table 4-5 lists the common attributes.
4, the timing constraint syntax
(1) period constraint
(2) offset constraint
(3) packet constraint
(4) local constraints
references
| Author | Blog |
| 1, Tian Yun Hsu Wen-bo | Xilinx FPGA Development Practical Guide 2nd Edition |
| 2, He Bin | Xilinx FPGA authoritative design guidelines |
| 3、Evening_FPGA | ISE UCF constraints in the preparation of documents |
