RTL Design (11)-Clock Gating

Clock gating

Stopping and restarting the clock signal at the negative edge or negative level of the clock signal can avoid glitches of the clock signal and avoid problems such as shortening the clock cycle.

There are two ways: negative edge register and negative level latch.

The clock gating using the latch method is better: (1) The area of ​​the latch is small; (2) The latch is level triggered, and the arrival time of the en signal can be more arbitrary.

Program example

The program implements a latch clock gating circuit.

clock_gating.v

`timescale 1ns / 1ps

// Company: 
// Engineer: 
// 
// Create Date: 2020/12/19
// Author Name: Sniper
// Module Name: clock_gating
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 


module clock_gating(
    input clk,
    input en,
	output clk_out
);

wire latch_out;

assign latch_out = clk==0 ? en : latch_out;
assign clk_out = latch_out & clk;


endmodule

tb_clock_gating.v

`timescale 1ns / 1ps

// Company:
// Engineer:
//
// Create Date: 2020/12/19
// Author Name: Sniper
// Module Name: tb_clock_gating
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//


module tb_clock_gating;

//input
reg clk;
reg en;


//output
wire clk_out;



initial
begin
    clk = 0;
    en = 0;

	#100;
    en = 1;
	#100;
    en = 0;

	#28;
    en = 1;
	#33;
    en = 0;

	#66;
    en = 1;
	#88;
    en = 0;

end

//clock
always #5 clk = ~clk;



//DUT
clock_gating DUT
(
    .clk(clk),
    .en(en),
    .clk_out(clk_out)
);

initial
begin
    $dumpfile("tb_clock_gating.vcd");
    $dumpvars(0,tb_clock_gating);
end

initial #500 $finish;

endmodule

Simulation results

vcs -R clock_gating.v tb_clock_gating.v