Design of 3-8 decoder based on vhdl

1. Design requirements

1. The three decoding input terminals A, B, and C correspond to 2, 3, and 4 of the development board as ON DIP
2. EN is the enable terminal (active low), corresponding to pin 1 on the development board, which is represented as ON DIP
3. Y is decoding output, 8-bit vector type. D3 to D10
4. Input adopts level switch, decoding output adopts LED indicator to display
   5) Decoding table is as follows:
   
   Two code experiment

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY decoder_38 IS
PORT(A,B,C,EN:IN std_logic;
            y:OUT std_logic_vector(7 DOWNTO 0));
END decoder_38;
ARCHITECTURE behav OF decoder_38 IS
 SIGNAL indata:std_logic_vector(2 DOWNTO 0);
BEGIN
 indata<=C&B&A;
 PROCESS(indata,EN)
 BEGIN
     IF(EN='0')THEN
       CASE indata IS
         WHEN"000"=>y<="11111110";
         WHEN"001"=>y<="11111101";
         WHEN"010"=>y<="11111011";
         WHEN"011"=>y<="11110111";
         WHEN"100"=>y<="11101111";
         WHEN"101"=>y<="11011111";
         WHEN"110"=>y<="10111111";
         WHEN"111"=>y<="01111111";
         WHEN OTHERS=>y<="XXXXXXXX";
END CASE;
ELSE y<="11111111";
END IF;
END PROCESS;
END behav;

Three complete circuit diagrams

Four simulation results

Five experimental results
(a) input is 000, LED0 is illuminated

(b) input is 001, LED1 is illuminated

© input is 010, LED2 is illuminated

(d) is 011, and LED3 is illuminated

(e) is 100 , LED4 glows

(f) Input is 101, LED5 glows