When learning EDA for the first time, everyone was troubled by looking for tools . Some tools either do not have licenses or cannot be set up, or they cannot be used. Are you worried that someone will use them in the future?
Therefore, through my own experience, I recommend everyone to give you a learning process and a process used in the industry, the purpose of which is of course for employment (for bragging in resumes).
Enough talk, let's start explaining
For beginners, it is recommended to use the following process
1 The tool when coding is recommended ultraedit + ( VHDL , verilog syntax highlighting patch)
2 debug tools use debussy of novas When you use it, you will think it is a really useful tool.
3 Simulation tool utility The newer version of modelsim supports more languages, and now the latest version supports assertion based verification and systemc
The latest version is also said to support the verification function of system verilog .
4 FPGA synthesis tools have nothing to say. Synopsys FPGA and syplify are estimated to cover most of the market. Of course, they are also useful for mentors, but for
These two tools are easy for learners to acquire and install.
5 For the latter tools, just use xilinx ise and quanters
Explain in detail
1. Coding tool, since almost all ASIC design houses are Unix platforms , it is naturally the most commonly used editor tool vi in Unix. Of course, you can also use ultraedit + (VHDL, verilog syntax highlighting patch), but because it is Under the windows platform, so you have to write the program
Via FTP or other tools, to unix.
2. The debussy of the debug tool novas is based on the unix/linux platform. It is strongly recommended to use it to save eyesight.
3. The simulation tool industry generally uses tools from two companies, Cadence's LDV (logic design verification) and synopsys' VCS series
The LDV market has a relatively large proportion because it includes two simulation tools, nc-verilg and verilog-xl, which we are all familiar with. verilog-xl is
The inventor of the verilog language was specially designed for verilog, so it belongs to a mother. nc-verilog is an improved version of verilog-xl, better suited for functional verification.
However, verilog-xl is still used more in gate-level simulation (so-called netlist simulation or later post simulation), because nc-verilog compares
Slow in these projects. As for which tool to choose, it depends on what the director of the company likes. Some companies use everything, and some companies use it according to the project.
The testbench of my project is implemented with vera, so it is more unified with synopsys, at least it can reduce the unknown factors between tools,
Caused inexplicable bugs. But it should be noted that nc-verilog is said to have the ability to sgin-off when tape-out, that is, when you save your design , the chip manufacturer has to see if your design is not. After passing the verilog-xl simulation, I have heard of these. Specifically, because I am also a rookie, some of the words may not be accurate. If there are people in the industry, I will give more advice. Modelsim is not used by no one, because its ability is really mixed simulation, so when your design has two kinds of verilog and vhdl, it seems to have the largest market share. In addition, this thing, because it provides free licenses to major campuses , so everyone has it.
4 The synthesis tool is synopsys design compiler, and you have other options. The key is that you use other tools, and the chip manufacturer does not dare to take over your work. But I almost forgot, magama's phsical synthesis tool is also used by some people. He seems to integrate the layout of the latter part. The example I know so far is that some project groups of TI company reuse it, because my teacher has From TI headquarters. This thing seems to be more suitable for technology below 0.18, synopsys now has the same tool, called synopsys phsical synthesis, the application seems to be bigger than magama, because my internship company is using it, and my Indian colleagues are using it, huh, still And I want the English manual, because the toutou gave him the Japanese version.
5 I know some of the tools in the latter stage, but they are not too specific. I will talk about it next time. I am only talking about the tools of the cell-based design process. If they are fully customized, they are very different.