FPGA study notes 4.2 - sequence detection FSM detection

Design ideas

Design a sequence of 4 consecutive 0s or 4 consecutive 1s to detect FSM , define a long sequence, and output the number of detected 4 consecutive 0s and 4 consecutive 1s respectively. Displays the number of consecutive 0s and consecutive 1s 

Schematic

Function module code:

module lianxi(clk,clr,x,z,out0,out1);
input clk,clr,x;
output reg z; 
output wire[6:0] out0;
output reg[6:0] out1;
reg[3:0] out70,out71;  
reg[2:0] state;
parameter  S0=3'b000,S1=3'b001,S2=3'b010,S3=3'b011,S4=3'b100,S5=3'b101,S6=3'b110,S7=3'b111; 

function[6:0] fout7;
		input[3:0] fin4;
		case(fin4)
			4'H0:fout7=7'b1000000;   
			4'H1:fout7=7'b1111001;  
			4'H2:fout7=7'b0100100; 
			4'H3:fout7=7'b0110000;   
			4'H4:fout7=7'b0011001;  
			4'H5:fout7=7'b0010010;  
			4'H6:fout7=7'b0000010; 
			4'H7:fout7=7'b1111000;  
			4'H8:fout7=7'b0000000;
			4'H9:fout7=7'b0011000;  
			default:fout7=7'b1111111;
    endcase
endfunction

task Bto7;
input[3:0] tin4;
output reg[6:0] tout7;
  case(tin4)
    4'H0:tout7=7'b1000000;   
    4'H1:tout7=7'b1111001;  
    4'H2:tout7=7'b0100100; 
    4'H3:tout7=7'b0110000;   
    4'H4:tout7=7'b0011001;  
    4'H5:tout7=7'b0010010;  
    4'H6:tout7=7'b0000010; 
    4'H7:tout7=7'b1111000;  
    4'H8:tout7=7'b0000000;
    4'H9:tout7=7'b0011000;  
    default:tout7=7'b1111111;
    endcase
endtask
	
always @(posedge clk or posedge clr)  
begin
if(clr) begin state<=S0;out70<=0;out71<=0;z=1'b0; end      
else begin
case (state)
S0:begin if(x) begin state<=S4;z<=1'b0; end else begin state<=S1;z<=1'b0; end end
S1:begin if(x) begin state<=S4;z<=1'b0; end else begin state<=S2;z<=1'b0; end end
S2:begin if(x) begin state<=S4;z<=1'b0; end else begin state<=S3;z<=1'b0; end end
S3:begin if(x) begin state<=S4;z<=1'b0; end else begin state<=S0;z<=1'b1;out70<=out70+1; end end
S4:begin if(x) begin state<=S5;z<=1'b0; end else begin state<=S0;z<=1'b0; end end
S5:begin if(x) begin state<=S6;z<=1'b0; end else begin state<=S0;z<=1'b0; end end
S6:begin if(x) begin state<=S7;z<=1'b0; end else begin state<=S0;z<=1'b0; end end
S7:begin if(x)  begin state<=S4;out71<=out71+1;z<=1'b1; end else begin state<=S0;z<=1'b0; end end
default: begin state<=S0;z<=1'b0;end  
endcase
     end
end


assign out0=fout7(out70);
always @(out71) begin
		Bto7(out71,out1);
end 

endmodule

Test module code: 

`timescale 1 ps/ 1 ps
module lianxi_vlg_tst();
reg clk;
reg clr;
reg x;                                             
wire [6:0]  out0;
wire [6:0]  out1;
wire z;
                        
lianxi i1 (
	.clk(clk),
	.clr(clr),
	.out0(out0),
	.out1(out1),
	.x(x),
	.z(z)
);
initial                                                
begin                                                                                           
$display("Running testbench");  
clr=0;clk=0;x=0;
#1 clr=1;
#1 clr=0;
#20 x = 1; #4;
#20 x = 0; #4;
#20 $stop;
end                                                    
initial
$monitor($realtime,,,"x=%b out0=%b out1=%b",x,out0,out1); 
always                                                                 
begin                                                  
   #1 clk =~ clk;                                        
end                                          
endmodule

Running the graph: