Hardware Study Notes 2--Power Supply Circuit Design
Written at the front: This note comes from Wang Gong’s hardware engineer training course. Students who want to learn hardware can go to Tencent Classroom and search directly. The following is my summary of knowledge points. When learning hardware, I recommend that you read more about components. Manual, more hands-on practice.
1. LDO design
1.1 LDO principle
Definition
LDO is the abbreviation of Low Dropout Regulator, which means low dropout linear voltage regulator.
- Low voltage drop means: the input voltage-output voltage value is relatively low.
- Linear means: MOS is basically in a linear working state.
- The voltage regulator means: within the normal VIN range, the output VOUT is stable at a fixed value, and this fixed value is the voltage value we want. For example, if the VIN voltage is 4.4~5V, VOUT always maintains a 3.3V output.
The
LDO usually consists of 一个基准电压源an 一个取样输出电压error amplifier and a series adjustment tube
. The amplifier is used to control the voltage drop of the voltage regulator to maintain the required output voltage value.
The output voltage is divided by the feedback resistor to the input terminal of the error amplifier. When the output voltage is higher than the set value, the internal circuit will change the driving voltage, causing the conduction voltage drop of the tube to increase, thus reducing the output voltage.
Adjustment principle:
LDO normally works at point P1
. The load resistance decreases, the output current increases, the output voltage Vo decreases, and V DS increases. The operating point moves to P2,
the feedback voltage decreases, and the amplifier output causes V GS to increase and V DS to decrease. ID increases . The working point moves to P3, the difference between VF and V REF approaches 0, and the system returns to balance.
Improvement: The change lines of P1, P2, and P3 in the figure below should be moved to the left as a whole to the variable resistance area. In the figure, they are placed on the right for ease of viewing. Of course, there are also LDOs that are adjusted in the constant current area.
- All voltage regulators use
反馈回路a (Feedback Loop) to keep the output voltage stable. - The feedback signal will change in gain and phase after passing through the loop. The stability of the loop is determined by the total phase offset at the unit gain frequency.
- Circuits that introduce feedback must consider loop stability issues. The deeper the negative feedback, the easier it is to self-oscillate.
- In order to improve the operating stability of the amplifier under deep negative feedback conditions, the generally used vibration elimination method is frequency compensation (phase compensation)
1.2 LDO parameters
Dropout Voltage Dropout voltage refers to the minimum voltage drop
that the input voltage, V IN , must be higher than the required output voltage, V OUT , for the LDO to achieve normal voltage regulation.
If V IN falls below this value, the linear regulator operates in dropout and no longer regulates the desired output voltage.
To regulate the desired output voltage, the feedback loop will control the drain-source resistance R DS . As V IN gradually approaches V OUT , the error amplifier will drive the gate-source voltage V GS to increase negatively to reduce R DS and thereby maintain regulation.
However, after the error amplifier output reaches saturation, it cannot drive V GS to increase further in the negative direction. R DS has reached its minimum value. Multiplying this R DS value by the output current I OUT will give you the dropout voltage.
Linear (voltage) regulation rate
Linear regulation rate (Line regulation) defines the impact of input changes on the output, that is, under a certain load, the ratio of the output voltage change to the input voltage change.
The linear adjustment rate formula is:
that is, the output change is greater than the input change
To reduce the linear adjustment rate, you can increase the amplification factor of the error op amp and increase the transconductance of the adjustment tube.
LDO的线性调整率越小, the smaller the impact of input voltage changes on the output voltage, the better the performance of the LDO.
Load regulation
Load regulation refers to the change in output voltage under a given load change. The load change here is usually from no load to full load .
The load regulation formula is:
That is, the change from no-load voltage to full-load voltage is greater than the change from no-load current to full-load current.
- Load regulation reflects the performance of the pass components and the closed-loop DC gain of the regulator. The higher the closed-loop DC gain, the better the load regulation.
- Like the linear regulation rate, the load regulation rate is related to the amplification factor A of the error amplifier and the transconductance of the adjustment tube. In order to reduce the load regulation rate, the values of these two quantities can be increased.
LDO的负载调整率越小, indicating that the LDO has a stronger ability to suppress load interference.
Power supply rejection ratio
One of the advantages of LDO is that it can attenuate the voltage ripple generated by the switching power supply, and an important parameter that can attenuate the voltage ripple is the power supply rejection ratio (PSRR).
PSRR specifies the degree of attenuation of an AC signal of a specific frequency from the LDO input to the output.
Unlike the above two parameters, the larger the power supply rejection ratio, the better.
Transient response
Transient response is the maximum change in output voltage caused by a sudden change in load current. It is
a function of the output capacitor Co, its equivalent series resistance ESR, and the bypass capacitor Cb. The function of Cb is to improve the load transient response capability. It also serves as a high-frequency bypass for the circuit.
To achieve optimal transient response, the closed loop bandwidth must be as high as possible while ensuring sufficient phase margin to maintain stability.
Therefore, a larger bypass capacitor can be selected according to the diagram.
1.3 Application
Calculation of power and temperature rise
The parameters framed in the figure represent the degree of temperature rise when the power is 1w.
We can calculate the device power through the preset output current and voltage drop, and then get the temperature rise to determine whether this device can be selected.
The figure shows the change in output voltage when the output current changes. When the current reaches a certain level, the voltage will decrease rapidly.
Consideration of input and output capacitors. The main function of the input
capacitor is to filter the input of the regulator. In addition, the input capacitor also offsets the parasitic inductance effect introduced when the input line is long and prevents the circuit from self-oscillation. Therefore, the input end of the regulator is generally used Design of two capacitors connected in parallel.
较大的电容To provide filtering effect, generally choose left and 22uFright; 较小电容to provide oscillation elimination effect, generally choose it 0.1uF, and the position should be as close as possible to the input pin of the regulator.
Note: The effect of temperature on capacitor characteristics:
all capacitors need to be derated by 80%, and tantalum capacitors need to be derated by 50%.
Output Capacitance Much of a voltage regulator's performance is affected by its output capacitance. Among them, the capacitance value and ESR have the most important impact on the frequency response of the circuit. Improper selection of the output capacitor and ESR can easily cause self-oscillation of the circuit.
Generally, the 22uFleft and right capacitors are selected; smaller capacitors can eliminate high-frequency noise, and are generally selected.0.1uF
The location should be as close as possible to the output pin of the regulator. When selecting the capacitor, you also need to consider the impact of temperature on the capacitance value and ESR. You should ensure that the circuit is stable within the entire temperature range.
Because the LDO control loop has limited bandwidth, the output capacitor must provide most of the load current required for fast transients.
Actual circuit
phase margin
When the gain is zero, the value of the phase minus 180° must be greater than 45°, otherwise it will affect the stability of the circuit. This value is determined by the ESR of the output capacitor.
Some notes on PCB board drawing
: 1. Capacitors should be placed nearby in order of large first and then small.
2. The width of the input/output wiring path and the number of layer-changing vias must meet the power supply current;
3. Large GND pads must be drilled with holes. , to facilitate heat dissipation, a solder mask window must be opened on the back.
4. The input/output GND should be connected together as much as possible to maintain complete return flow.
2. DC-DC design
2.1 DC-DC principle
principle
The circuit continuously switches the input voltage to form a PWM level. When the voltage reaches zero, it uses a freewheeling diode, a freewheeling capacitor, and a freewheeling inductor to reduce the voltage reduction speed until the power is turned back on and the level changes. The middle value of is the output voltage.
The functions are discussed separately:
- When the switch is turned on, energy is transferred from the input to the output, and the current rises diagonally;
- When the switch is turned off, the inductor, load, and diode form a freewheeling loop, and the current begins to decrease linearly; when it reaches a certain level, the switch is reopened;
- High-frequency turning on and off forms a stable output voltage.
Simplified schematic diagram
The role of each device:
1. The input capacitor (C1) is used to stabilize the input voltage;
2. The output capacitor (C2) is responsible for stabilizing the output voltage;
3. The box diode (D1) acts as an inductor when the switch is open Provide a current path;
4. The inductor (L1) is used to store the energy to be transmitted to the load.
When is the output a boost and when is a buck?
We can know from the formula Vo=Vin*D/(1-D) that when D=0.5, Vo=Vin; when D<0.5, Vo<Vin; when D>0.5, Vo>Vin.
Synchronous rectification
Synchronization is a new technology that uses special power MOSFETs with extremely low on-state resistance to replace rectifier diodes to reduce rectification losses. It can greatly improve the efficiency of DC/DC converters and there is no dead zone voltage caused by Schottky barrier voltage. Power MOSFET is a voltage-controlled device, and its volt-ampere characteristics when turned on are linear. When using a power MOSFET as a rectifier, the gate voltage must be synchronized with the phase of the rectified voltage to complete the rectification function, so it is called synchronous rectification.
Compare options:
-
Efficiency
Synchronization efficiency is high, asynchronous efficiency is low. -
Cost
Synchronization cost is high, asynchronous cost is low. -
Reliability
Synchronization reliability is high, asynchronous reliability is low.
2.2 Introduction to DC-DC parameters
The power efficiency eta
efficiency formula is:
P out : output power
P d : level conversion chip power loss
Example of loss comparison between 5V output and 3V output:
Mode Burst Mode-CCM
At light load, the PWM converter can automatically switch to a "low power" mode to minimize battery current consumption. This mode is sometimes called “PFM” – but is actually a fixed frequency (PWM) converter that switches on and off intermittently.
According to the waveforms on the left and right, we can see that the one on the left is the classic PWM mode, and the picture on the right is the waveform of the PWM jump mode at light load or time. The frequency of PWM in the jump mode is reduced, so the switching loss is reduced.
Feedback Control
When the output voltage increases, the feedback voltage V FB increases, and the output of the negative feedback error amplifier decreases. Therefore, the duty cycle decreases . The output voltage is pulled back so that V FB = V REF . There is only one control loop to regulate the output.
The following parameters are a TPS54331 chip as an example:
- BOOT: The pin connected to the bootstrap capacitor. The generally connected capacitor is 0.1uF.
- VIN: input voltage pin, the input voltage is 3.5-28V
- EN: Start pin, the default is the output voltage when the voltage is greater than 1.25V
- SS: Slow start pin to reduce the output level arrival time
- VSENSE: feedback voltage pin
- COMP: loop pin, changes phase margin and gain margin
- GND: Ground pin
- PH: output pin
- special pin
Typical circuit
2.4 DC-DC design points
Calculation of the EN pin resistance
is shown in the figure as shown in the manual.
- V EN defaults to 1.25V , which means that the chip can output the level only after the input voltage VIN rises to 1.25V, and its value can be changed by changing the resistance of Ren1 and Ren2.
- V START means that the chip will not output voltage until the input voltage rises to V START .
- V STOP means that when the input voltage drops to V EN , the chip will stop outputting voltage
For example, the input voltage is 12V, the output voltage is 3.3V, and the maximum current is 3A. I specify that the voltage can only output 3.3V after the voltage rises to 8V. If the voltage drops to 7V, it will stop outputting 3.3V. Then V START = 8V,
V STOP = 7V , Into the formula,
the resistance value of Ren1 is about 333k
and the resistance value of Ren2 is about 58.8K
SS pin soft start capacitor setting
What the above manual says is that you can set the slow start time of the output voltage by setting the capacitor value connected to the SS pin .
The slow start time is the time for the output voltage to reach the target voltage from 0.
It is best to set the slow start time between 1ms and 10ms. The maximum capacitance cannot exceed 27nf. Put the capacitance into the formula to calculate the time to 10.8ms.
Note: Setting the capacitance too high will cause the power supply to start too slowly and the CPU to start abnormally. If it is too small, the power supply may not start.
Generally you can choose 22nF or 10nF
Calculation of VIN pin input capacitance
The input pin end generally needs to be connected to a filter capacitor to filter the voltage. The manual recommends choosing 10uF, X5R or X7R material. It actually uses two 4.7uF capacitors in parallel, and the ESR is 2m ohms. , the maximum output current is 3A, and a 0.01uF capacitor is used for high-frequency filtering.
The range of filtered ripple voltage is calculated by the following formula:
- I O(MAX) : Maximum output current, mentioned above is 3A
- C BULK : Parallel capacitor value, mentioned above is 10uF
- f SW : switching frequency, checked in the manual is 570kHz
- ESR MAX : The ESR value of the capacitor is 2m ohms. It can be obtained by adding it to the formula. The filtered ripple voltage range is 143mV.
In addition to the filtered ripple voltage, it is also mentioned above that the ripple current should be considered, which is I O(MAX) /2, which is 1.5A.
The general calculation formula is as follows:
Current effective value calculation:
- dc is the duty cycle, usually 0.5
- Since the above has been multiplied by 1000, there is no need for unit conversion in the denominator. If the value brought into C MIN is 10uF, the calculated maximum filtered ripple voltage is 131.58mv.
In actual use, the capacitor selected is generally a 47uF tantalum capacitor, a 10uF ceramic capacitor and a 0.1uF small capacitor in parallel, which can filter out high-frequency and low-frequency noise and have a particularly small ESR.
Calculation of output voltage
The output voltage can VSENSEbe set through the pin, which is the negative feedback pin of the chip
By setting the values of R5 and R6, the output voltage can be set. The calculation method is as follows:
The manual says that R5 and R6 can set the output voltage value. The selected resistor value R5 is 10.2K and R6 is 3.24. The 0 ohm resistor of R4 can be left unsoldered when welding the circuit to test the circuit stability.
Selection of filter inductor
Calculation method:
- Vinmax: maximum output voltage, 12V
- Vout: output voltage, 3.3V
- Io: output current, 3A
- Kind: a coefficient, 0.1-0.4, generally 0.3 is selected. For detailed explanation, please refer to the manual.
- f SW : switching frequency, 570kHz
Into the formula we get L1=4.66uH, so we can choose the commonly used 4.7uH inductor.
The influence of sense value:
- High inductance – small ripple current
- Low inductance – high ripple current
- Ripple current is a factor that determines core loss
- Important parameters for reducing power inductor losses include not only switching frequency but also ripple current.
Supplementary formula: The above is the calculation formula for
ripple current I LPP , temperature rise current IL (RMS) , and peak current IL (PK) . Add in the inductor 4.7uH, and get I LPP as 1.16A, IL (RMS) as 3.01A, IL (PK) is 3.58A.
Temperature rise current refers to the current when the temperature does not exceed 40 degrees.
Output capacitor selection
Effect of output capacitance:
- Effect on output voltage ripple
- Effect on output voltage after load transient
The calculation formula of the ripple voltage is as follows:
equal to the inductor ripple current × the resistance of the output capacitor
The chip manual explains as follows:
What the manual means is that the angular frequency of the generally selected output capacitor is less than the shear frequency, and the shear frequency generally does not exceed 1/5 of the switching frequency. In this chip, the shear frequency is set at 25kHz.
Therefore, the output capacitance is calculated as follows:
- R o is the output impedance (3.3/3 = 1.1)
- F CO(MAX) is the shearing frequency (25kHz)
The minimum capacitance value obtained is 5.8uF.
In addition to the capacitance, we also need to consider the ripple voltage, the ESR of the capacitor, and the ripple current of the capacitor. The calculation formula is as follows:
D: duty cycle (0.5)
V OPP : ripple voltage, we expect the maximum value to be 25mv, so The ESR max can be obtained as 21.5m ohms
Freewheeling diode
Manual description:
This means that the freewheeling diode is placed in reverse between the PH pin and GND. If the conduction voltage drop is 0.5V, then the maximum input voltage must be greater than V IN (MAX) +0.5. Pay attention to the power loss of the diode. The problem is to choose a diode with smaller loss as much as possible. The typical circuit uses a diode with a reverse voltage of 40V, a conduction current of 3A, and a conduction voltage drop of 0.5V.
Loop design calculations
Loop design indicators: shear frequency, phase margin, gain margin - the definitions, meanings and empirical values of these indicators are given below:
- Cut frequency:
- Definition: Some documents call it crossover frequency, which refers to the frequency corresponding to when the loop gain is 0dB;
- Significance: The higher the shear frequency, the faster the response speed, but it is more likely to cause loop instability or oscillation; if the shear frequency is too low, the transient response of the loop will be insufficient, which may lead to abnormal output voltage;
- Experience value: Usually the shear frequency is designed to be 1/10~1/20 of the switching frequency; systems with insufficient transient response often have shear frequencies lower than 10KHz, and the loop is in an over-compensated state at this time;
- Transient response: It mainly represents the change in output voltage caused by load change. The worse the transient response, the greater the change in output voltage caused by the same load change;
- Phase/Gain Margin:
- Definition: Phase margin - when the loop gain is 0, the corresponding difference between the signal phase and 180°; Gain margin - when the signal phase is 0, the corresponding negative gain amount;
- Significance: Characterizes the stability of the switching power supply. If the phase margin or (and) gain margin is insufficient, the system may enter an unstable or oscillating state due to the effects of temperature, PCB layout and individual device differences
; - Experience value: For a sufficiently stable switching power supply design, the phase margin should generally be ≥45° and the gain margin should be ≤-10dB.
The first step is to select the shear frequency.
The second step is to calculate the gain and phase boost required at the shear frequency.
Cutting frequency is 25kHz (F co )
According to the manual:
the phase margin should be greater than 60
Phase loss calculation formula:
C O is the output capacitor, R ESR is the ESR of the output capacitor, described as follows:
Therefore C O = 54uF, R ESR = 1m ohm
Therefore:
the phase lift PB is:
PM is the phase margin 60, PL= 83.52
so PB = 53.52
Find PB, then the following values can be obtained
Therefore the loop can be determined:
R z = 29.14k
C z = 928pF
C p = 51pF
2.5 DC-DC design considerations
Switching frequency considerations
- The advantage of a higher switching frequency is: the same output capacitor ripple is smaller and the dynamic response is better. The disadvantage is that switching losses are higher and the energy of switching noise is higher.
- The advantages of lower switching frequency are: lower switching losses and lower switching noise energy. The disadvantage is that the same output capacitor has larger ripple and worse dynamic response.
Based on the above characteristics, the operating frequency of the intermediate value 500KHZ is selected.
Operating temperature
Pay attention to the operating temperature of the power chip when designing. (If the operating temperature is not met, it may cause abnormal output voltage)
Mode selection:
When the power module is used under light load conditions, the BURST/Pulse-Skipping mode can be used to improve conversion efficiency.
When using the continuous mode under heavy load, the ripple is small and the dynamic response of the power supply is good (if the BURST/Pulse-Skipping mode is used, the ripple of the output power supply will be large and the dynamic response is poor).
A few points to note
输出电压设定 : Note that if there are multiple channels or multiple chips connected in parallel, pay attention to whether the internal pull-up resistors are also connected in parallel. If there is any calculation, divide the internal pull-up resistor by the number of parallel connections.
软启动的设置: Set the SS capacitance of several power modules according to the order required for voltage startup. Make it produce the required power-on sequence. Note: If the capacitance is set too high, the power supply will start too slowly and the CPU will start abnormally. If it is too small, the power supply may not start up
.
Pay attention to the low-temperature output deviation of the power supply. The output voltage will change if the temperature is too low or too high.
Note that the efficiency of the power supply has a great relationship with the input voltage and output power. If the load is only 10% of the rated power, the efficiency of the power supply is not high. The efficiency is highest at 50% of the rated power. The smaller the input-output pressure difference, the higher the efficiency.
