Digital IC front-end study notes: cross-clock domain signal synchronization

Single-bit Signal Synchronization Basics

When the input signal of a flip-flop does not meet the setup time (setup time) and hold time (hold time), the output will be in a metastable state, that is, the output is neither 1 nor 0, and is in an uncertain value. When the metastable state When the output is used as the input of other logic gates, it may cause chain transmission of metastable states, so some method must be used to prevent flip-flops from entering metastable states.

In a digital system with only one clock (called a single-clock-domain digital system), you can ensure that the setup and hold times meet timing requirements by controlling the delay of the combinational logic circuit between the two flip-flops. But when the output of one clock domain flip-flop is used as the input of another clock domain flip-flop, the two clocks have no correlation, and the metastable state at this time needs other methods to avoid.

The figure below shows a way to solve this problem, which is to insert two cascaded D flip-flops at the end of the output of the CLK_B clock domain. At this time, the output of Q_BS1 may appear in a metastable state, but before the next clock edge comes, the metastable state will stabilize, and at this time, Q_BS2 will most likely not appear in a metastable state. But when the CLK_B clock is very fast, Q_BS2 may still appear metastable. At this time, you can consider increasing the number of cascaded D flip-flops. In practical applications, it is sufficient to use two-level triggers to tap.

Signal Synchronization Rules

When signals are synchronized, several rules need to be followed.

Signals that cross clock domains must come directly from the register outputs of the source clock domain. If the signal comes from combinatorial logic instead of directly from flip-flops, races and hazards can be created, an example is given in the figure below.

At the beginning, the two inputs of the AND gate are 1 and 0, and the output c is 0. When a changes from 0 to 1 and b changes from 1 to 0, the final output c is still 0, but a and b may be short The time is always in the 1 state, causing the output c to be 1 by mistake for a period of time. If the rising edge of CLK_B happens to occur at this time, then the glitch signal 1 will be passed to the subsequent stage, making d and e appear a certain width False signals, which we don't want to see. If the register using the CLK_A clock domain is inserted behind the AND gate, then the glitch on c will not appear, thus not affecting the normal operation of the circuit.

Synchronizers are implemented using dedicated flip-flops in the logic cell library. The special-purpose flip-flops mentioned here have high drive capability and high gain ( $\text{[math]}$ ), which will make them enter the stable state faster, so using them can speed up the speed of the circuit getting out of the metastable state.

One output signal, avoiding the use of multiple synchronization devices for synchronization. What this sentence means is that you cannot use multiple synchronizers to synchronize a signal to multiple points in another clock domain, because the synchronizers will cause the signal to be delayed by 1 to 2 cycles, and if there are multiple synchronizers, then the result may be There will be inconsistencies (even if the end result is consistent), which will cause errors in downstream systems.

Multi-bit output signals avoid using multiple synchronization devices to synchronize separately. What we discuss in this article are all single-bit signals, mostly control signals. When multi-bit signals need to be synchronized, we cannot use the method in this article. The reason is the same as c. The multi-bit results may have unstable combinations. May lead to errors (this can also be avoided by using Gray code encoding, because Gray code only changes one bit at a time). How to synchronize so many Bit signals? We can use asynchronous FIFO, or other methods such as handshake protocol to synchronize.

Signal Synchronization Advanced

According to the relative speed of the two frequency domain clock speeds, we divide the synchronization of single-bit signals into two cases. For these two cases, different methods are required for synchronization.

Asynchronous control signals in the fast clock synchronous slow clock domain

在这种情况下，可能会出现异步信号在自己的慢时钟域中只维持了一个时钟的有效时间，但在快时钟域却被采样了多次，这可能会导致目标时钟域误以为有多个连续的有效控制信号（这里和之前的信号沿检测文章中要求输出一个单周期宽度的检测信号类似，见https://blog.csdn.net/weixin_45791458/article/details/128690161?spm=1001.2014.3001.5501）。

这里采用的方法为在两级同步器后再加一个级别，然后利用第三个同步器的低电平和第二个同步器的高电平译码出一个周期的高电平。

input sig_a;
input clkb;
input rstb;
 
reg sig_a_d1,sig_a_d2,sig_a_d3;
wire sig_a_posedge;
 
assign sig_a_posedge=sig_a_d2&!sig_a_d3;
 
always@(posedge clkb,negedge rstb)
begin
    if(!rstb)
    begin
        sig_a_d1<=1'b0;
        sig_a_d2<=1'b0;
        sig_a_d3<=1'b0;
    end
    else
    begin
        sig_a_d1<=sig_a;
        sig_a_d2<=sig_a_d1;
        sig_a_d3<=sig_a_d2;
    end
end

慢时钟域同步快时钟域下的异步控制信号

用慢时钟同步快时钟域下的控制信号带来的问题是可能在慢时钟到来之前，快时钟的控制信号已经失效，这样就丢失了控制信号，显然造成了功能错误，信号波形如下图所示。对于这个问题，常见的是使用握手机制。

握手机制（一）

我们通过握手机制，人为锁存快时钟域的控制信号，然后通过同步器穿越边界，使慢时钟域采样到信号，再通过同步器反馈给快时钟域，接着快时钟域释放当前控制信号，这时就可以响应下一个控制信号，原理图如下所示。

其中，数据从adat输入，左下角应该是一个不是一个简单的触发器，而是可以根据反馈信号锁存adat的触发器，锁存后的信号为adat1，这个信号通过两级同步器进入慢时钟域，并将反馈信号（这里是信号本身）同步会快时钟域，表示信号已收到，可以取消快时钟域的锁存信号了，并等待下一个adat有效信号的到来。

用Verilog HDL实现的快时钟域的锁存代码如下。

module adapt_gen(input aclk,rest_b,adat,abdat2,output reg adat1);
    always@(posedge clk,negedge rest_b)
        if(!reset_b)
            adat1<=1'b0;
        else
            if(abdat2)
                adat1<=1'b0;
            else
                adat1<=adat;    
endmodule

这种方法不能解决快时钟域信号在两个慢时钟域信号间多次翻转的问题。握手机制默认了这种情况不存在，也就是说，在设计时，必须保证快时钟域两个有效信号间的最小时间限制。这个最小值是反馈回路的延迟和第一个同步器恢复无效状态的时间之和。

握手机制（二）

我们还可以将快时钟域异步信号连接到一个D触发器的时钟端，而输出端连接至高电平，然后通过两级同步器连接至慢时钟域，慢时钟域收到信号后给出反馈信号，复位D触发器和第一个同步器，如下图所示。

当异步信号有效沿来临时，D触发器的输出q1被置为1，此时q1可能不满足第一个同步器的建立时间要求，导致q2出现亚稳态，但在Synch_out端，亚稳态不会出现（同步装置的原理），输出被反馈回到复位端，与输入信号的低电平一起复位前两个触发器，这样使得输出信号的宽度为一个慢时钟域时钟周期。

以上内容来源于《Verilog高级数字系统设计技术和实例分析》、《SOC设计方法与实现》和《Verilog HDL高级数字设计》

Digital IC front-end study notes: cross-clock domain signal synchronization

related articles

Single-bit Signal Synchronization Basics

Signal Synchronization Rules

Signal Synchronization Advanced

Guess you like