First, the design requirements of
a design capable of displaying a date, hours, minutes and seconds of digital electronic clock, and the whole point of the timekeeping function.
2, can be manually corrected, time division time and date value, a time period of 24 hours, when the correction function, can be separately when separate points and correction, it is corrected to the standard time;
3, having a counting process timekeeping function, when the first 10 seconds of time to reach full beep timekeeping point; in order to ensure a stable and accurate timing reference signal to provide time hands shall 1HZ standard crystal oscillator generates a signal of a crystal oscillator circuit, minutes, seconds six decimal counter, while twenty-four binary counter.
Second, the experimental design and analysis
2.1 works
digital clock is the "hour", "minute", "second" display to the timing device human visual organs. Its timing cycle of 24 hours, displaying full scale 23:59:59, when there should be another school function and timekeeping functions. Thus, a basic circuit mainly by the decoding digital clock display, "hour", "minute", "second" counter, when the correction circuit, and an oscillator circuit timekeeping composition. Dry the second signal generator circuitry, "hour, minute, second" counter, a decoder and a display, when the correction circuit, the whole point timekeeping circuit. A second signal generator of the system time base signal, which directly determines the accuracy of the timing system, using the quartz crystal oscillator is generally applied to achieve a frequency divider. The second signal into a standard "second counter", "second counter" use of binary counter 60, every 60 seconds total transmit a "partial pulse" signal, which will serve as the "sub-counter" clock pulses. "Minute counter" also uses binary counter 60, accumulated every 60 minutes, send a "pulse" signal, which will be sent to "the counter." "Counter" the 24-ary timers that can be achieved for a total of 24 hours a day. The decoding circuit outputs the display state "when", "minute", "second" counter by the seven-segment display decoder decodes, displayed through the six seven segment display LED. Generating a pulse signal according to the output state timing when the system chime circuit then triggers the tone generator implemented timekeeping. When correction is used to "hour", "minute" display digital proofreading of the circuit adjustment.
Displayed by the digital electronic clock oscillator, a frequency divider counter, decoder, timer circuit and the like. Wherein the second oscillator and divider standard signal generator, different from the binary counter, a decoder and a display timing system. Signal into the second counter counts, the accumulation result 'when ,,' ,, minutes to 'seconds' figures shown. 'Is' displayed by the binary counter 24, a decoder, a display configuration, the 'points', 'second' respectively displayed by the binary counter 60, a decoder, a display configuration. Can be whole point of time, the timing when an error occurs, the correction circuit may be used when the time correction, correction points.
FIG overall framework 2.2
2.3 oscillator
time base signal is usually generated are high frequency oscillator, can be used to make it over the timing of the "second" signals, to be done by the frequency divider. Stages and each stage of the frequency divider of the frequency division number is determined according to the frequency of the time base. For example, currently use more electronic quartz clock timing signal 32768HZ of this signal can be obtained after 15 cycles 1S "second" signal. Other frequencies can also be used in the time base signal, and then determining the frequency division numbers selected good choice of integrated circuit.
2.3.1 1HZ by a second pulse signal composed of a quartz oscillator
when the timing signal generated 32768Hz quartz crystal oscillator 15 frequency. 14 is a binary counter selection \ divider CMOS integrated circuit cc4060, it can be obtained by the 14 points of the signal frequency. Then 74LS74 TTL integrated circuits of the dual-clock D flip-flop form a flip-flop type counter, completion of the first frequency divider 15, to obtain a red signal period of 1s.
And a frequency divider circuit connected to the oscillator and the pin arrangement of FIG cc4060:
Third, the functional design and implementation
1, the digital clock frequency is divided, two second counters are employed to complete the 60-ary counter 74LS161. Second signal generator is the core of digital electronic clock, which determines the accuracy and stability of the signal generator and sub-precision signal generator. "Sec" counter 60 binary counter. To achieve this counter 100 is a modulo two counter 74LS161 integrated sheet size configuration. Points "binary counter 60 is a counter. With the" second "counter is made as two sheets scale integration counter 74LS161. The two 74LS161 with the method according to the second counter 10 connected to a binary up counter, then the" second " the method of connecting the counter circuit 100 can be realized with the binary counter and then the "second" method of binary counter 60 to achieve specific implementation follows:..
. 2, digital clock counter using 24-ary complete when two 74LS163 counter 24 is a binary counter. accomplish this modulo counter is constituted by two sheets scale integration counter 74LS90. with "minute", "second" counter as first two-ary counter 24 is connected to the adding counter 74LS90, then two counter 74LS90 with "second" method to be implemented the access counter binary counter 100 when the counter status is "2QD2QC2QB2QA, 1QD1QC1QB1QA = 0010,0100", requires counter to zero. by 2QB, 1QC fed opposed the number of pulses so that two 74LS90 while the counter is cleared, this constitutes the binary counter 24 embodied as shown below:
3, this course is designed Focus is on non-leap year leap year for Otsuki, Satsuki, (counting only average year 29 days) control the number of days in February, so the number of days required to be fed back to a count of three cases when the specific circumstances of the month, respectively, for binary 00 , February 29 to 01, 10 denotes days, Satsuki 30 days, 31 days Otsuki. controls the number of days from the upper portion of "day" in accordance with FIG three values returned. 30, 31, respectively, to the counting when cleared, cleared since 74LS192 asynchronous manner, the maximum value of the display 29, 30 respectively, and then clear again counted as embodied in FIG.:
4, the counting section into digital clock monthly counting section and a feedback section. The above two part using a selector selected from 8 to 16, in combination (> 12 months) 1 selectors (Proteus selected in a selector 16, can be simplified), two feedback requires two binary 1 selectors 16 . The following part is actually two 12-scale counter. For a display, to select a specific implementation used for feedback as shown below:
Fourth, the simulation program of FIG.
V. Appendix (source code and virtual simulation Download)
due to the limited space and the corresponding code simulation map has been uploaded (including program and curriculum design), there is a need of self-created:
https://download.csdn.net/download/ qq_44699923 / 12240923
Attached to a digital clock curriculum design, there is a need of self-created:
https://download.csdn.net/download/qq_44699923/12240936
Someone asked to see a side note, the reason is .pdsprj file, because I was editor of the new version of proteus, if you want to just use proteus8.0 .dsn file compiler that you can get .dsn resave the file.
