Digital logic and digital system design (Yuan Xiaoping) MOOC reference answers

Lecture 1 Introduction Lecture 1 Introduction-Unit Testing

1. Question: In the development of modern electronic technology, integrated circuit devices are currently in the () stage. Options: A: Discrete components B: Integrated circuits C: Large-scale integrated circuits D: Very large-scale integrated circuits Answer: [Very large-scale integrated circuits] 2. Question: The development of modern electronic technology is in the () stage. Options: A: Theoretical foundation B: Discrete components C: Integrated circuit era D: Vacuum tube Answer: [Integrated circuit era] 3. Question: Correct description of the high and low levels of digital signals (). Options: A: Each corresponds to a voltage range B: Each corresponds to a certain voltage value C: The high level is 5V D: The low level is 0V Answer: [Respectively corresponds to a voltage range] 4. Question: Integrated circuits follow The degree of integration is divided into (). Options: A: Small scale B: Medium scale C: Large scale D: Ultra large scale Answer: [Small scale; Medium scale; Large scale; Ultra large scale] 5. Question: The representative chips of modern integrated circuits are (). Options: A: Single chip microcomputer B: FPGA C: DSP D: SOPC Answer: [Single chip microcomputer; FPGA; DSP; SOPC] 6. Question: The application scope of electronic technology, including () and other aspects. Options: A: Daily life B: Industrial and agricultural production C: Military and national defense D: Aerospace Answer: [Daily life; Industrial and agricultural production; Military and national defense; Aerospace] 7. Question: The main content of this course includes (). Options: A: Combinational logic circuit B: Sequential logic circuit C: Pulse generation and shaping D: FPGA E: HDL F: Digital system design method Answer: [combinational logic circuit; sequential logic circuit; pulse generation and shaping; FPGA; HDL; digital system design method] 8. Question: Among the following devices, which one is a digital device (). Options: A: Gate circuit B: Storage circuit C: Combinational circuit D: Sequential circuit E: FPGA Answer: [Gate circuit; Storage circuit; Combinational circuit; Sequential circuit; FPGA] 9. Question: The characteristics of analog signals are reflected in ( ). Options: A: Not easy to transmit B: Not easy to store C: Not easy to calculate D: High power consumption Answer: [Not easy to transmit; not easy to store; not easy to calculate] 10. Question: The characteristics of digital signals are reflected in () . Options: A: Low anti-interference B: Easy to transmit C: Easy to store D: Easy to calculate Answer: [Easy to transmit; easy to store; easy to calculate] 11. Question: Physical quantities that are continuous in time and amplitude are called numbers Signal options: A: Correct B: Wrong Answer: [Correct] 12. Question: Physical quantities that are continuous in time and amplitude are called analog signal options: A: Correct B: Wrong Answer: [Correct] 13. Question : Analog signals are easy to transmit but not easy to store. Option: A: Correct B: Wrong Answer: [Wrong] 14. Question: Digital signals are easy to transmit and easy to calculate. Option: A: Correct B: Wrong Answer: [Correct] 15. Question: Digital signals can be represented by 0 and 1. Options: A: Correct B: Wrong Answer: [Correct] 16. Question: 1 of the digital signal is greater than 0 of the digital signal. Options: A: Correct B: Wrong Answer: [Wrong] 17. Question : In modern electronic technology, analog-to-digital converters can be used to convert analog signals and digital signals into each other. Options: A: Correct B: Wrong Answer: [Correct] 18. Question: The English word for CPLD is (). Answer: [Complex Programmable Logic Device] 19. Question: The English name of FPGA is (). Answer: [Field Programmable Gate Array] 20. Question: The signal is information (). Answer: [Carrier] 21. Question: Signals in electronic circuits include analog signals and (). Answer: [Digital signal] 22. Question: Electronic circuits, including analog circuits and (). Answer: [Digital circuit]

[Assignment] Lecture 1 Introduction Lecture 1 Introduction-Unit Assignment

1. Question: Use the knowledge you have learned to come up with an idea for designing an electronic product. The requirements are: (1) Product application background; (2) Function and principle; (3) Use product block diagrams and text to describe it. Scoring rules: [Mainly examine students’ imagination and creativity. The key is ideas and creativity. Don’t worry too much about whether it can be realized based on the student’s block diagram. (1) Product application background (creativity), 30 points; (2) Function and principle description, 20 points. If there is creativity and the description of the principle and block diagram is reasonable, a full score of 50 points will be given; if the creativity is average and the description of the principle and block diagram is average, a score of 30 points will be given. In other cases, points will be awarded as appropriate. ] 2. Question: As an electronic engineer, what issues should you consider when designing electronic products? Scoring rules: [It is recommended to evaluate from the perspectives of market (10 points), efficiency (10 points), technical standards (10 points), ethics (10 points), and law (10 points). If it can be reasonably described from the perspective of market, efficiency, technical standards, ethics, and law, 50 points will be given; if the description is general or not comprehensive enough, a maximum of 30 points will be given. 】

Lecture 2 Number System Conversion Lecture 2 Number System Conversion-Unit Test

1. Question: ( ) is generally used to convert decimal numbers into binary numbers. Options: A: Multiply by 2 and round to integer B: Multiply by 10 and round to the integer C: Multiply by 2 and round to the integer D: Multiply by 10 and round to the integer Answer: [Multiply by 2 and round to the integer] 2. Question: Convert the decimal number 18 to octal yes( ). Options: A:20 B:22 C:24 D:21 Answer: 【22】 3. Question: Any hexadecimal number can be represented by at least ( ) binary number. Options: A:1 B:2 C:4 D:16 Answer: [4] 4. Question: The decimal number corresponding to the signed binary number 11010 expressed in two's complement is ( ). Options: A:+10 B:-10 C:+6 D:-6 Answer: [-6] 5. Question: Convert the binary number (11001.11)B into a decimal number ( ). Options: A: 25.75 B: 19.75 C:25.6 D:20.75 Answer: [25.75] 6. Question: Convert the binary number (110 1101 1010) B into a hexadecimal number (). Options: A: EB2 B: 9EA C: 6DA D: 6CA Answer: 【6DA】 7. Question: Converting the binary number (1101.101) B into an octal number is ( ) Options: A: 15.625 B: 15.5 C: 15.25 D: 15.75 Answer: 【15.5】 8. Question: Decimal number – 8 of 25 The two's complement representation is (11100111)B, right? Options: A: Correct B: Wrong Answer: [Correct] 9. Question: For a signed binary number, the highest bit represents the sign bit, and the rest represents the numerical bits, so a 4-bit signed binary represented by two's complement The number 1001 represents the decimal number –1. Is it right? Options: A: Correct B: Wrong Answer: [Wrong] 10. Question: Write an octal number as (783.64), right? Options: A: Correct B: Wrong Answer: [Wrong] 11. Question: The maximum decimal number that can be represented by an 8-bit unsigned binary number is 256. Is it right? Options: A: Correct B: Wrong Answer: [Wrong]

[Homework] Lecture 2 Number System Conversion Lecture 2 Number System Conversion - Unit Assignment

1. Question: Convert binary numbers to decimal, octal, or hexadecimal. 1110101 Scoring rules: [10 points for each pair of decimals (1110101)2 = (117)10 = (165)8=(75)16] 2. Question: Convert decimal numbers into binary numbers, octal and hexadecimal . 29.5 Scoring rules: [Each pair of bases is worth 10 points (29.5)10= (11101.1)2 =(35.4)8=(1D.8)16] 3. Question: Write the original code and complement code of each of the following numbers and complement. -10110 Scoring rules: [10 points for each machine code [X] original = 110110; [X] inverse = 101001; [X] complement = 101010; ] 4. Question: Given [N] complement = 10111, find [N ]Original scoring rules: [[N]Original=11001]

[Homework] Lecture 3 Coding System Lecture 3 Coding System - Unit Assignment

1. Question: Try using 8421 code and Gray code respectively. (1010110)2 Scoring rules: [Each question corresponds to 10 points each for 8421 and Gray code, a total of 20 (1010110)2 = (1000 0110) 8421 (1010110)2 = (1111101) Gray code] 2. Question: Remaining 3 from the following code converted to decimal number. (1) 011010000011 (2) 01000101.1001 Scoring rules: [ (1) (0110 1000 0011) remaining 3 codes = (350) 10 (2) (0100 0101.1001) remaining 3 codes = (12.6) 10 ] 3. Question: Complete the following Conversion between codes: (1) (1000100100010101.0101)8421=( )10; (2) (1010001110000111) remainder 3=( )8421 Scoring rules: [ (1000100100010101.0101)8421=( 8915.5 )10; (101000 1110000111) more than 3= (0111 0000 0101 0100 )8421 ] 4. Question: Can a set of numbers 11001001 stored in the computer be expressed as the following BCD code? If so, what is the value of the decimal number represented? (1) 8421BCD (2) 5421BCD (3) 2421BCD (4) The remaining 3 code scoring rules: [ (1) The 8421BCD code cannot be used to represent (2) The corresponding decimal value of 5421BCD is 96 (3) The corresponding decimal value of 2421BCD is 63 (4) The decimal value corresponding to the remaining 3 codes is 96]

Lecture 3 Coding System Lecture 3 Coding System-Unit Test

1. Question: The decimal number 25 is represented by 8421BCD code ( ). Options: A: 00100101 B: 1001010 C: 10000101 D: 10101 Answer: [ 00100101 ] 2. Question: The result of converting (01000101.1001)8421BCD into the remainder code is ( ) Options: A: 01000101.1100 B: 01001000 .1001 C:01111000.1100 D :01001000.1100 Answer: [01111000.1100] 3. Question: The 4-digit cyclic code of decimal 5 is ( ) Options: A: 0101 B: 1101 C: 1110 D: 0111 Answer: [ 0111 ] 4. Question: Convert the decimal number 69.75 to The result of binary number and 8421BCD is () Options: A: 1000110.1100, 01101001. 1100 B: 1010011.1101, 1101001. 111101 C: 1000101.0011, 01101001.01110101 D: 1000101 .1100, 01101001.01110101 Answer: [1000101.1100, 01101001.01110101] 5. Question: The decimal number 895.7 corresponds The remaining 3 codes are ( ) Options: A: 1000 1001 0110.1110 B: 1011 1100 1000.1010 C: 0001 1001 1010.1110 D: 1000 1001 1010.0111 Answer: [ 1011 1100 1000.1010 ] 6. Question: The code that meets the Hamming distance of 1 is ( ). Options: A: 8421BCD code B: Remainder 3 code C: Gray code D: 2421BCD code Answer: [Gray code] 7. Question: Among the following codes, which one is BCD code ( ). Options: A: 8421BCD code B: Remainder 3 code C: Gray code D: 2421BCD code Answer: [8421BCD code; Remainder 3 code; 2421BCD code] 8. Question: The following reliability code is (). Options: A: 8421BCD code B: Remainder 3 code C: Gray code D: Parity check code Answer: [Gray code; parity check code] 9. Question: What is the equivalent of the binary number (10011) 2 ( ) option : A:19 B: (23)8 C: (00011001)8421 D: (01001100) 3 more digits Answer: [19; (23)8; (00011001)8421; (01001100) 3 more digits] 10. Question: Among the following codes, the one that belongs to the authorized code is (). Options: A: 8421BCD code B: Remainder 3 code C: 5421BCD code D: 2421BCD code Answer: [8421BCD code; 5421BCD code; 2421BCD code] 11. Question: Parity check code can only detect errors, but cannot correct them. Options: A: Correct B: Wrong Answer: [Correct] 12. Question: The remaining 3 codes are not BCD codes Options: A: Correct B: Wrong Answer: [Wrong] 13. Question: There is a number 10010101. When it is used as an 8421 BCD code, it Equivalent to the decimal number __. Answer: 【95】

Lecture 5 Algebraic Simplification of Logical Functions Lecture 5 Algebraic Simplification of Logical Functions – Unit Test

1. Question: Algebraic method simplifies the expression of a logical function, usually () Options: A: AND or expression B: AND or NOT C: AND NOT D: OR and NOT Answer: [AND OR expression] 2. Question: algebraic simplification

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Options: A:

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Answer: 【

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] 3. Question: Simplify logical functions

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Options: A:

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Answer: 【

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] 4. Question: Simplify function

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Options: A:

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Answer: 【

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】 5. Question: Method to prove that two logical functions are equal () Options: A: By calculating the same truth tables of two logical functions respectively; B: Judging that C is the same by deducing the simplest formulas of the two functions. : Judge by drawing the same logic diagrams of the two logic functions respectively. D: When all combinations of the input variables are in the same order, judge the answer by drawing the same output values of the two output waveforms: [By calculating the two values respectively. The same method as the truth table of the logic function;; When all the input variables are combined in the same order, it can be judged by drawing the output values of the two output waveforms respectively] 6. Question: The basic expression form of the function is () Options: A: AND-OR formula B: NAND-NAND formula C: OR-AND formula D: OR-NOT-OR NOT formula Answer: [AND-OR formula; OR-AND formula] 7. Question: The AND-OR formula of a logical function must be the most Short form options: A: Correct B: Wrong Answer: [Wrong] 8. Question: The simplest form of a logical function must be AND or OR options: A: Correct B: Wrong Answer: [Correct] 9. Question: The simplest form of a logical function must be AND or The basic expression form is the AND or expression, or the AND expression. Options: A: Correct B: Wrong Answer: [Correct] 10. Question:

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Answer: [1] 11. Question:

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Answer:【0】

[Homework] Lecture 5 Algebraic Simplification of Logical Functions Lecture 5 Algebraic Simplification of Logical Functions – Unit Assignment

1. Question: Convert the logical function to

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Transformed into AND-OR expression, AND-NOT-AND-FER expression, AND-OR-FEATURE, OR-AND expression, OR-NOR-OR-NF expression. Scoring rules: [10 points for AND-OR expression, 10 points for AND-NOT-AND-FER expression, AND-OR expression 10 points for non-form, 10 points for or-and, or 10 points for non-or non-form. Pay attention to labeling each formula, and there must be a process, otherwise you will not get points.

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] 2. Question: Will

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Reduce it to the simplest AND or formula. Scoring rules: [ (1) Reference answer

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,50 points. (2) The form of the simplest form may be different, but as long as the conditions of the simplest form are met. (3) The answer must have a process, otherwise points will be deducted. 】

[Homework] Lecture 4 Basic Operation Rules of Logical Algebra Lecture 4 Basic Operation Rules of Logical Algebra – Unit Assignment

1. Question: Use inversion rules and duality rules to write

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The inverse function and dual function of . Scoring rules: [20 points for inverse functions and 20 points for dual functions. Note that the written results cannot be changed.

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] 2. Question: Known function

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, try to use truth tables, Karnaugh maps, and logic diagrams (basic logic gates) to represent them. Scoring rules: [Truth table (20 points), Karnaugh map (20 points), logic diagram (20 points). Other points will be determined based on the answers to the questions.

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】

Lecture 4 Basic Operation Rules of Logical Algebra Lecture 4 Basic Operation Rules of Logical Algebra – Unit Test

1. Question: The following is not a basic logical relationship () Options: A: AND logic B: Or logic C: Non-logical D: XOR logic Answer: [XOR logic] 2. Question: The variables of the logical function cannot be expressed () Options: A: High and low states of voltage B: True and beautiful C: On and off of switch D: Male and female Answer: [True and beautiful] 3. Question: The form of describing the relationship between logical functions is ( ) Options: A: Expression B: Logic diagram C: Truth table D: Waveform diagram Answer: [Expression; logic diagram; truth table; waveform diagram] 4. Question: and

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Equality has () option: A:

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Answer: 【

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;

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;

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] 5. Question: AND logic, OR logic, and non-logic are the basic logical relationship options: A: Correct B: Wrong Answer: [Correct] 6. Question: AND or NOT, AND NOT, XOR NOT are the compound logical relationship options : A: Correct B: Wrong Answer: [Correct] 7. Question:

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Options: A: Correct B: Wrong Answer: [Correct] 8. Question: Compound logical relations include AND or NOT·, NAND·, OR NOT, NOT and other logical relations. Options: A: Correct B: Wrong Answer: [Wrong] 9. Question:

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Answer: [1] 10. Question:

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Answer: 【1】

[Homework] Lecture 6: Simplifying the Karnaugh map of a logical function Lecture 6: Simplifying the Karnaugh map of a logical function – unit homework

Tips: This section contains strange chapters with the same name. 1. Question: Expand the following functions into the sum of minimum terms

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Scoring rules: [10 points for writing the final minimum expression of F=Σm(0,1,2,3,6,10,12,13,14,15), and points will be deducted for intermediate steps as appropriate] 2. Question: Use cards Karnaugh map converts the following functions into the simplest "AND or" expression F(A,B,C)=∑m(0,1,2,4,5,7) Scoring rules: [ 1. Fill in the Karnaugh map ( 8 points)

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2. Draw Carnot Circle (6 points)

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3. Write the simplest AND or expression (6 points)

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】 3. Question: Use Karnaugh map to convert the following functions into the simplest "AND or" expression F(A,B,C,D)=∑m(0,2,3,5,7,8,10, 11)+∑d(14,15) Scoring rules: [

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1. 10 points for filling in the Karnaugh diagram 2. 10 points for drawing the Karnaugh circle 3. 10 points for the simplest sum or expression

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】 4. Question: Use Karnaugh map to convert the following functions into the simplest "AND or" expression F(A,B,C,D)=∑m(0,1,2,5,6,7,8, 9,13,14) Scoring rules: [

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1. 10 points for filling in the Karnaugh diagram 2. 10 points for drawing the Karnaugh circle 3. 10 points for writing the simplest expression (there is also an answer) F=

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] 5. Question: Use Karnaugh map to convert the following functions into the simplest "AND or" expression F(A,B,C,D)=∑m(0,1,3,5,6,7,8, 9,13,14) Scoring rules: [

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1. 10 points for filling in the Karnaugh diagram 2. 10 points for drawing the Karnaugh circle 3. 10 points for writing the simplest expression (there is also an answer) F=

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】

[Homework] Lecture 7 Basics of Logic Gates Lecture 7 Basics of Logic Gates – Unit Assignment

1. Question: Given the waveforms of the input signals A and B and the waveforms of the output Y1, Y2, Y3, and Y4 as shown in the figure, try to determine what kind of logic gate each is, draw the corresponding logic gate diagram symbol, and write the corresponding Logical expression. Scoring rules: [What kind of logic gates are Y1, Y2, Y3, and Y4 (15 points each, 60 points in total), and draw the corresponding logic gate diagram symbols, and write the corresponding logical expressions (10 points each, 60 points in total) 40 points, no points will be given if one of the logical symbols and expressions is wrong; only if the logic gate is answered correctly, this part can be scored).

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】

Lecture 7 Basics of Logic Gates Lecture 7 Basics of Logic Gates – Unit Testing

1. Question: The logic gate with the function of "0 comes out of 1 and 1 comes out when all 0 comes out" is (). Options: A: NAND gate B: NOR gate C: XOR gate D: EXCLUSIVE OR gate Answer: [NOR gate] 2. Question: Logic gate circuit with the function of "0 out of 1, all 1 out in 0" function yes( ). Options: A: NOR gate B: NAND gate C: AND gate D: OR gate Answer: [NAND gate] 3. Question: A four-input NAND gate has a combination of input variable values whose output is 0 There are ( ) species. Options: A:15 B:1 C:3 D:7 Answer: [1] 4. Question: A gate circuit with two input terminals. When the input is 1 0, the gate circuit whose output is not 1 is ( ). Options: A: NAND gate B: OR gate C: NOR gate D: XOR gate Answer: [NOR gate] 5. Question: The basic logic gate circuit has (). Options: A: AND gate B: OR gate C: NOT gate D: AND or NOT gate Answer: [AND gate; OR gate; NOT gate] 6. Question: What is () a composite logic gate circuit? Options: A: AND or NOT B: XOR gate C: AND gate D: NAND gate Answer: [AND or NOT; XOR gate; NAND gate] 7. Question: All integrated logic gates have input terminals for two or more. Options: A: Correct B: Wrong Answer: [Wrong] 8. Question: Composite gates can be constructed using AND gates, OR gates, and NOT gates. Options: A: Correct B: Wrong Answer: [Correct] 9. Question: Logic gate circuit is the most basic unit in digital logic circuit. Options: A: Correct B: Wrong Answer: [Correct] 10. Question: A four-input NAND gate has 15 input variable value combinations whose output is 1. Options: A: Correct B: Wrong Answer: [Correct] 11. Question: If it needs to be implemented

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The logical relationship requires () 2-input AND gates, a 2-input OR gate and a NOT gate to form the answer: [(Any one of the following answers is correct) 2; both] 12. Question: Can "1 out of 0" be achieved , all 0 out 1" function gate circuit is () gate. Answer: [or not]

[Homework] Lecture 9 MOS Integrated Gate Circuit Lecture 9 MOS Integrated Gate Circuit – Unit Assignment

1. Question: The CMOS circuit is as shown in the figure. It is known that the input waveforms A, B, and C are as shown in figure (b), R=10kW, please draw the waveform at F terminal. Scoring rules: [Write expressions (2 situations, 15 points each, 30 points in total), waveform diagram (20 points, no points will be given if one state is wrong. No points will be given if the expression is incorrect).

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】 2. Question: The circuit composed of CMOS transmission gate and inverter is as shown in the figure. Try to draw the waveform of the output UO under the action of the waveform in figure (b) (UI1=10V UI2=5V). Scoring rules: [The output waveform and input waveform correspond to 5 situations, each worth 10 points, a total of 50 points.

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】

[Homework] Lecture 8 TTL Integrated Gate Circuit Lecture 8 TTL Integrated Gate Circuit – Unit Assignment

1. Question: To realize the logical relationship shown at the output terminals of each TTL gate circuit in the figure, are the connections of each gate circuit correct? If incorrect, please correct it. Scoring rules: [Judge whether the 4 circuit connections are correct (5 points each, 20 points in total). The wrong circuits need to be modified (10 points each, 30 points in total, only 3 need to be modified). If it is correct, check the circuit again. Are the modifications correct?

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] 2. Question: The circuit is as shown in Figure (a), and the waveform of its input variable is as shown in Figure (b). Try to determine during which periods the light-emitting diodes in the picture will light up. Scoring rules: [ (1) 10 points for correctly writing the expression; (2) Enter 16 codes and get the corresponding output level (2 points for each case, 32 points in total); (3) Determine the time when the diode lights up Paragraph (4 points for each paragraph, 8 points in total); (4) No points will be given if the expression is incorrect.

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】

Lecture 9 MOS Integrated Gate Circuit Lecture 9 MOS Integrated Gate Circuit – Unit Test

1. Question: The redundant input terminal of the integrated CMOS NAND gate can be connected to (). Options: A: Positive terminal of power supply B: Ground of power supply C: Grounded through resistor D: Floating Answer: [Positive terminal of power supply] 2. Question: The power supply voltage range of CMOS circuit is large, about ( ). Options: A: -5V~+5V B:3~18V C:5~15V D:+5V Answer: [3~18V] 3. Question: CMOS integrated circuits contain () tubes. Options: A:PMOS B:MOS C:TTL D:NMOS Answer: [PMOS; NMOS] 4. Question: Compared with TTL integrated circuits, CMOS integrated circuits have () advantages. Options: A: Wide operating voltage range B: Low power consumption C: Strong load capacity D: Fast speed E: Strong anti-interference ability Answer: [Wide operating voltage range; low power consumption; strong load capacity; strong anti-interference ability ] 5. Question: The redundant input terminal of the integrated CMOS NOR gate circuit should be (). Options: A: low level B: high level C: grounded through a 1K resistor D: connected to the power supply through a 1K resistor Correct answer: [low level; grounded through a 1K resistor] 6. Question: What are the differences between TTL and CMOS integrated circuits? NOT gate, its idle input terminal can be left floating. Options: A: Correct B: Wrong Answer: [Wrong] 7. Question: The load capacity and anti-interference ability of CMOS circuits are stronger than those of TTL circuits. Options: A: Correct B: Wrong answer: [Correct] 8. Question: The redundant input terminal of the integrated CMOS circuit can be left floating, which is equivalent to being connected to a high level. Options: A: Correct B: Wrong Answer: [Wrong] 9. Question: The redundant input terminal of the integrated CMOS AND gate circuit should be connected to () level. Answer: [High] 10. Question: Compared with TTL integrated circuits, the most prominent advantage of CMOS integrated circuits is (). Answer: [(Any one of the following answers is correct) low power consumption; low power consumption]

Lecture 8 TTL Integrated Gate Circuits Lecture 8 TTL Integrated Gate Circuits – Unit Test

1. Question: The power supply voltage of the TTL circuit is ( )V. Options: A: -5V~+5V B:3~18V C:5~15V D:+5V Answer: [+5V] 2. Question: If a TTL XOR gate is used as an inverter, then the A and B input terminal should be: ( ). Options: A: The B input terminal is connected to high level, and the A input terminal is used as the inverter input terminal. B: The B input terminal is connected to low level, and the A input terminal is used as the inverter input terminal. C: Two inputs, A and B. terminals are connected in parallel and used as the input terminal of the inverter D: cannot be realized Answer: [B input terminal is connected to high level, and A input terminal is used as the input terminal of the inverter] 3. Question: The output terminals of ( ) can be directly connected in parallel Together, the "wired AND" logic function is realized. Options: A: TTL NAND gate B: Tri-state gate C: OC gate D: XOR gate Answer: [OC gate] 4. Question: ( ) has been widely used in computer systems, and one of its important uses is to form Data Bus. Options: A: Tri-state gate B: TTL NAND gate C: XOR gate D: OC gate Answer: [Three-state gate] 5. Question: OC gate can realize () function options: A: Line AND B: Level Conversion C: Reduce power consumption D: Increase speed Answer: [Line AND; Level conversion] 6. Question: TTL OC gate can implement "wired AND" logic function options: A: Correct B: Wrong Answer: [Correct] 7. Problem: TTL integrated circuit NAND gate, its idle input terminal cannot be left floating. Options: A: Correct B: Wrong Answer: [Wrong] 8. Question: 74LS series products are the mainstream of TTL integrated circuits and are the most widely used. Options: A: Correct B: Wrong Answer: [Correct] 9. Question: The 74LS series integrated circuits are TTL type. Options: A: Correct B: Wrong Answer: [Correct] 10. Question: OC gates can not only implement the "bus" structure, but also form AND or NOT logic. Options: A: Correct B: Wrong Answer: [Correct] 11. Question: The load capacity of a TTL circuit is expressed by the fan-out coefficient. The fan-out coefficient represents the number of gate circuits in the integrated circuit. Options: A: Correct B: Wrong Answer: [Wrong] 12. Question: The TTL NAND gate with open integrated electrode is also called () gate. Answer: [OC] [Assignment] Lecture 10 Analysis and Design Methods of Combinational Circuits Analysis and Design Methods of Combinational Logic Circuits - Unit Assignment 1. Question: Use NAND gates to design a majority voting circuit with four variables. When the input variables A, When 3 or more of B, C, and D are 1, the output is 1, and when the input is in other states, the output is 0. Scoring rules: [1. The truth table is as follows: 20 points

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2. The function expression is: 10 points

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3. The logic diagram is: 20 points

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] 2. Question: Write the logical function expression in the figure below, and simplify it into the simplest AND or expression.

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Scoring rules: [Y1 expression 20 points (written 10 points, simplified result 10 points)

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Y2 expression 30 points (10 points per step)

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] Lecture 10 Analysis and Design Methods of Combinational Circuits Analysis and Design Methods of Combinational Logic Circuits - Unit Test 1. Question: Use NAND gates and NOT gates to design a three-digit even checker, that is, when there are three digits The output is 1 when there is an even number of 1s, otherwise it is 0. Assume that the three inputs are A, B, and C respectively, and the output is F, then the expression of the output signal F is ( ). Options: A:

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Answer: 【

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] 2. Question: Regarding the function of the circuit shown below, what is the correct description ( ).

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Options: A: As long as one variable in the input variable ABC has a value of 1, the output will be 1. B: As long as 2 or more variables in the input variable ABC have a value of 0, the output will be 1. C: As long as two or more variables in the input variable ABC have the same value, the output is 1. D: When the values of the three variables in the input variable ABC are the same, the output is 1. Answer: [When the values of the three variables in the input variable ABC are the same, the output is 1. 】 3. Question: For the circuit shown in the figure below, if an XOR gate is used to implement the circuit function, at least ( ) 2-input XOR gates are required.

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Options: A:1 B:2 C:3 D:4 Answer: [2] 4. Question: The expression that corresponds to the danger that may occur in a logic circuit is ( ) Options: A:

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Answer: 【

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] 5. Question: The function of the combinational logic circuit shown in the figure below is ( ).

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Options: A: Convert 8421 code to remainder 3 code B: Convert 8421 code to 2421 code C: Convert binary code to Gray code D: Convert binary code to 8421 code Answer: [Convert 8421 code to remainder 3 code] 6. Question: The circuit as shown in the figure In , the minimum term expression of Y(A,B,C,D) is ( ).

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Options: A:Y=Σm(1,2,3,4) B:Y=Σm(0,1,2,3,4) C:Y=Σm(5,6,7) D:Y=Σm( 3,5,6,7) Answer: [Y=Σm(5,6,7)] 7. Question: The TTL circuit is shown in the figure below, and the output can be achieved

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The circuit is ( ).

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Options: A:A (The pull-up resistor is appropriate) B:B C:C D:D E:E Answer: [A (The pull-up resistor is appropriate)] 8. Question: The relationship between the output and input of a combinational logic circuit can be expressed by ( ). Options: A: Truth table B: State table C: State diagram D: Logical expression Answer: [Truth table; logical expression] 9. Question: Function

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, when the value of the variable is , risk-taking will occur. Options: A:B=C=1 B:B=C=0 C:A=1，C=0 D:A=0，B=0 Answer: [B=C=1 ; A=1，C=0 ; A=0, B=0] 10. Question: Which of the following are the steps in designing a combinational logic circuit? ( ) Options: A: Transform and simplify the logic expression according to the selected gate type B: List the logic function expression C: List the circuit truth table according to the actual engineering requirements D: Draw the logic circuit Answer: [ According to the selected gate type, transform and simplify the logic expression; list the logic function expression; list the circuit truth table according to the actual engineering requirements; draw the logic circuit] 11. Question: Eliminate commonly used combinational logic circuits There are three methods for competing risks: discovering and eliminating possible complementary variable operations, adding gating control signals, and using filter circuits. ( ) Options: A: Correct B: Wrong Answer: [Correct] 12. Question: Combinational logic circuits are usually composed of logic gates and flip-flops. ( ) Options: A: Correct B: Wrong Answer: [Wrong] 13. Question: A circuit composed of logic gates is a combinational logic circuit. Options: A: Correct B: Wrong Answer: [Wrong] 14. Question: The stable output signal of a combinational logic circuit at any time depends on . Answer: [Input signal at this moment] 15. Question: The output of a combinational logic circuit is only related to the current state, and has nothing to do with the input state of the circuit. Its basic unit circuit is . (Answers are separated by commas) Answer: [(Any one of the following answers is correct) Input, original, logic gate; Input, original, gate circuit] Lecture 11 Encoder Encoder - Unit Test 1, Question: 10 Line-4 line priority encoder 74LS147 is a high order priority encoding circuit (

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highest priority), when the 74LS147 is working normally, if the input signal

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, then output

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for( ). Options: A:0110 B:1001 C:1111 D:0000 Answer: [1111] 2. Question: To design a binary encoding for 1000 symbols, at least ( ) binary digits are required. Options: A:3 B:10 C:1000 D:11 Answer: [10] 3. Question: The input of the 8-line-3-line priority encoder is

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, when the highest priority

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When valid, its output

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The value is . Options: A:111 B:000 C:010 D:101 Answer: [000] 4. Question: Only one input terminal of the circuit is valid at any time. Options: A: Binary decoder B: Ordinary binary encoder C: Seven-segment display decoder D: Priority encoder Answer: [Ordinary binary encoder] 5. Question: For 8-line-3 line priority encoder, the following The correct statement is (). Options: A: There are 8 input lines and 3 output lines B: There are 8 input lines and 8 output lines C: There are 3 input lines and 3 output lines D: There are 3 input lines and 8 output lines Answer: [There are 8 input lines and 3 output lines] 6. Question: After the 8-line-3-line priority encoder 74LS148 is powered on, its strobe output terminal outputs a low level, the reason may be ( ) option : A: There is a problem with the power supply B: No valid coding input C: The strobe input terminal is not connected to ground D: The extension terminal is not connected to high level Answer: [No valid coding input] 7. Question: 8-line-3-line priority encoder 74LS148 After the power is turned on, no matter how the coding input changes, all outputs are blocked at high level. The reason may be: ( ) Options: A: There is a problem with the power supply B: The coding input is invalid C: The strobe input terminal is not grounded D : The extension terminal is not grounded. Answer: [The strobe input terminal is not grounded] 8. Question: When two or more inputs of an ordinary encoder are valid signals at the same time, the output will have incorrect coding. ( ) Options: A: Correct B: Wrong Answer: [Correct] 9. Question: When 2 or more inputs are valid signals at the same time, the priority encoder will only encode the input with high priority. ( ) Options: A: Correct B: Wrong Answer: [Correct] 10. Question: The encoder can only encode one input signal at any time. ( ) Options: A: Correct B: Wrong Answer: [Correct] 11. Question: After the 8-line-3-line priority encoder 74LS148 is powered on, if the encoding signal input is from

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The order is 01000101, then the encoding output is . Answer: [001] 12. Question: The characteristic of the priority encoder is that it allows multiple encoding signals to be input at the same time, but only one of the signals is encoded. Answer: [(Any one of the following answers is correct) highest priority; highest priority; highest priority; high priority] [Assignment] Lecture 11 Encoder Encoder-Unit Assignment 1. Question: Line 8-3 The line priority encoder 74LS148 is connected to the circuit shown in the figure below, and the function of the circuit is analyzed.

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Scoring rules: [4 points for each line of the truth table, 40 points in total, 10 points for function (5 points for the priority encoder)

Function: 10-4 lines 8421BCD code priority encoder] 2. Question: Try 74HC147 to design keyboard encoding circuit, ten keys

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Corresponding to decimal numbers 0~9 respectively, the output ABCD of the encoder is 8421BCD code. Requirements: Button 9 has the highest priority and has a GS working status mark to indicate that the button is not pressed and that button 0 is pressed.

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Scoring rules: [5 points for input definition, 5 points for output definition, 20 points for truth table (5 points will be deducted for each wrong one, until all deductions are completed), 5 points for circuit diagram input, 10 points for GS output, and 10 points for ABCD output (wrong) 5 points will be deducted for each one, until all deductions are made)

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Represents ten buttons, respectively representing 9 in the decimal number. The output of the encoder is A, B, C, D, and the working status flag GS. If a button is pressed, it is 1, and if no button is pressed, it is 0. The truth table is as follows:

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Circuit diagram:

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] [Homework] Lecture 12 Decoder Decoder - Unit Homework 1. Question: The combinational logic circuit composed of the 3-line to 8-line decoder 74LS138 and the gate circuit is as shown in the figure below. Among them, the input signal

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is the address line. Try writing the address realized by each output of the decoder.

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Judging rules: 【

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10 points for each correct output address, and the rest

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5 points for correct output address.

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] 2. Question: Given a combinational logic circuit, the input A, B, C waveforms and the output F1, F2 waveforms are as shown in the figure (the input waveform changes periodically according to this rule), list the truth table of the circuit, Write the minimum term output expressions of F1 and F2, and use 74LS138 to implement the circuit.

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Scoring rules: [Write a truth table (F1 (F2) will deduct 5 points for each wrong output, 10 points for two wrong outputs, a total of 20 points), F1 and F2 output expressions (5 points each), circuit diagram (address 5 points for terminal, 5 points for enabling, 5 points for each of the two outputs, 20 points in total)

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] Lecture 12 Decoder Decoder-Unit Test 1. Question: It is known that the input three enable terminals of the 74LS138 decoder

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, when the address code A2A1A0=011, the output Y7 ~ Y0 is ( ). Options: A: 11111101 B: 10111111 C: 11110111 D: 11111111 Answer: [ 11110111 ] 2. Question: If a decoder has 100 decoding output terminals, then the decoder address input terminals must have at least ( ). Options: A:100 B:6 C:7 D:8 Answer: [7] 3. Question: A 6-64 line decoder can be formed by using the 3-8 line decoder 74HC138, which requires ( ) piece of 74HC138. Options: A:10 B:9 C:8 D:7 Answer: [9] 4. Question: The output of a 4-bit input binary decoder should have ( ) bits. Options: A:1 B:4 C:8 D:16 Answer: [16] 5. Question: Assume that the input and output signals of a four-bit binary decoder with a valid low-level output are ABCD and

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,When the decoder works normally, if ABCD=0110, it will output

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= ( ) Options: A:Z B:0 C:1 D:X Answer: [1] 6. Question: The multi-channel data distributor can be implemented directly by ( ). Options: A: Encoder B: Multi-channel data selector C: Decoder D: Multi-bit adder Answer: [Decoder] 7. Question: The output status of the 4-line-10-line decoder is only F2=0. If the other output terminals are all 1, then its input status should be ( ). Options: A:1000 B:0100 C:0010 D:0001 Answer: [0010] 8. Question: Which of the following chips belongs to the decoder ( ) Options: A: 74LS148 B: 74LS138 C: 74LS48 D: 74LS42 Answer: [74LS138; 74LS48; 74LS42] 9. Question: The following can be used as data distributors ( ). Options: A: 74LS138 B: 74LS48 C: 74LS148 D: 74LS139 Answer: [74LS138; 74LS139] 10. Question: When the decoder implements a combinational logic function, it is based on the simplest AND or expression of the logic function. ( ) Options: A: Correct B: Wrong Answer: [Wrong] 11. Question: An n-bit binary decoder has

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an output terminal. ( ) Options: A: Correct B: Wrong Answer: [Correct] 12. Question: Decoder, as its name implies, translates high and low level signals into binary codes. Options: A: Correct B: Wrong Answer: [Wrong] 13. Question: Determine the implementation function

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The diagram shows the correct and incorrect circuit connections.

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Options: A: Correct B: Wrong Answer: [Wrong] 14. Question: Each output signal of the binary decoder is a minimum term of the input variable. ( ) Options: A: Correct B: Wrong Answer: [Correct] 15. Question: It is the reverse process of encoding. Answer: [Decoding] 16. Question: When using a decoder to implement the computer input/output interface address decoding circuit, if the decoder used has a 3-bit address code, it can control at most the console input/output device. Answer: [8] [Assignment] Lecture 15 Numerical Comparator Lecture 15 Numerical Comparator - Unit Assignment 1. Question: Use the numerical comparator 74LS85 and the necessary logic gates to design a remainder 3 code effective monitoring circuit. When the input is remainder When the code is 3, the output is 1, otherwise it is 0. Scoring rules: [The range of the remaining 3 codes is 0011~1100, which is implemented here with two 74LS85s and a NOR gate

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NOR gate (10 points), 74LS85 (1) A number with 3 remaining codes, B number 1100, cascade terminal 001, use F (A>B) output terminals each with 5 points, a total of 20, 74LS85 (2) A number Remainder 3 codes, B number 0011, cascade terminal 001, use F (A<B) output terminal 5 points each, total 20, ] 2. Question: 12-bit numerical comparator composed of 3 pieces of 4-bit numerical comparator 74LS85 wiring diagram. (Achieved by parallel comparison method) Scoring rules: [20 points for the correct connection of the 85(1) chip, 5 points will be deducted for each wrong cascade end and data end, until all deductions are made; 85(2) and 85(3) chips will be deducted for each 15 points for correct connection, a total of 30 points, 5 points will be deducted for each wrong cascade end and data end, until all points are deducted.

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] Lecture 15 Numerical Comparator Lecture 15 Numerical Comparator - Unit Test 1. Question: When using the 4-bit comparator 74LS85 to compare two four-bit binary numbers, compare the ( ) bits first. Options: A: Second highest B: Highest C: Lowest D: Second lowest Answer: [Highest] 2. Question: Analyze the combination circuit shown in the figure below. The output function expression and the logic function of the circuit are ( )

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Options: A:

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Answer: 【

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] 3. Question: Use the circuit shown in Figure (a) and the integrated four-digit digital comparator shown in Figure b to form a five-digit digital comparator. L, Q, and G are connected to the serial input terminals , , and 74LS85 respectively.

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Options: A:A>B;A<B;A=B B:A<B;A>B;A=B C:A>B;A=B;A B Answer: [A<B;A=B;A>B] 4. Question: To design an 8-bit numerical comparator, ( ) bits of data input and 3-bit output signals are required. Options: A:16 B:12 C:10 D:8 Answer: [16] 5. Question: Which of the following statements is wrong: ( ) Options: A: Numerical comparator can compare the size of numbers B: Decoder can also be used as Data distributor is used C: Encoders can be divided into ordinary encoders and priority encoders D: The circuit that implements the addition of two one-bit binary numbers is called a full adder Answer: [The circuit that implements the addition of two one-bit binary numbers is called Full adder] 6. Question: 74LS85 is a four-bit binary data comparator. If only 4-bit data comparison is performed, then the three cascade input terminals a<b, a>b, a=b should be: ( ) Options: A: ab is grounded, a=b is grounded B :ab is connected to high level, a=b is connected to high level C:ab is connected to high level, a=b is connected to ground D:ab is grounded, a=b is connected to high level. Answer: [ab is connected to ground, a=b is connected to high level] 7. Question: To use the equal output terminal of the comparator, you can use Which of the following functions are applied to ( ) Options: A: Judgment that two groups of numbers are less than B: Digital electronic lock C: Judgment of unequal conditions D: Judgment of unequal conditions Answer: [Digital electronic lock; Judgment of unequal conditions; No Judgment of equal conditions] 8. Question: Among the following logic circuits, which ones are combinational logic circuits ( ) Options: A: Encoder B: Decoder C: Numerical comparator D: Data selector Answer: [Encoder; Decoder; numerical comparator; data selector] 9. Question: The following ( ) are functionally a pair of inverse operations. Options: A: Decoder and encoder B: Decoder and data selector C: Decoder and data distributor D: Data selector and data distributor Answer: [Decoder and encoder; data selector and data allocator] 10. Problem: Numerical comparators can generally only compare whether two values are equal. Options: A: Correct B: Wrong Answer: [Wrong] 11. Question: The serial cascade expansion method of numerical comparators has a simple structure, but the operation speed is usually lower than the parallel expansion method. Options: A: Correct B: Wrong Answer: [Correct] 12. Question: When using the expansion of the numerical comparator, if a higher operating speed is required, the expansion method needs to be adopted. Answer: [(Any one of the following answers is correct) Parallel; Parallel connection] 13. Question: When using parallel connection to expand the numerical comparator, its characteristics are: circuit structure ( ), operating speed ( ). (Please use the answer, separated) Answer: [Complex, fast] [Homework] Lecture 14 Adder Lecture 14 Adder - Unit Assignment 1. Question: Please use 742LS83 to design a controllable remainder 3 code to 8421BCD code and 8421BCD code to remainder 3 code conversion circuit. When X=0, the 8421BCD code to the remainder 3 code is realized, and when X=1, the remainder 3 code is realized to 8421BCD code. Scoring rules: [ +1), complement operation.

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Analysis is 10 points, circuit diagram is 40 points, (carry input terminal is connected to X, 10 points; NOT gate is connected to A0A1, 10 points; 2. Question: The logic circuit composed of 4-bit adder 74LS283 is as shown in the figure. M and N are control terminals. Try to analyze the function of this circuit.

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Scoring rules: [The expression of B number is

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, worth 10 points, 5 points will be deducted for each wrong one; MN=00,

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, the output result is equivalent to S=I+0;MN=01,

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, the output result is equivalent to S=I+2; MN=10,

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, the output result is equivalent to S=I+3;MN=11,

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, the output result is equivalent to S=I+5. When MN=00~11, each B number value is 5 points, and the expression of S is 5 points, a total of 40 points] Lecture 14 Adder Lecture 14 Adder - Unit Test Tip: This section contains strange chapters with the same name. 1. Question: The input (A, B, C) output waveforms (X, Y) of a combinational logic circuit are as shown in the figure below, then its logical function is ( )

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Options: A: Encoder B: Half adder C: Full adder D: Decoder Answer: [Full adder] 2. Question: The four-bit carry lookahead adder 74LS283 improves the working speed because of ( ) option : A: The carry bits of each bit are passed in sequence B: It is a four-bit serial carry adder C: There are four full adders inside D: The carry bits of each bit are passed at the same time Answer: [The carry bits of each bit are passed at the same time] 3. Question: The figure below shows the logic circuit diagram of a series-connected full adder for adding two 4-bit binary numbers. The result of CoS3S2S1S0 after operation is ( )

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Options: A: 11000 B: 11001 C: 10110 D: 10101 Answer: [11000] 4. Question: The logical relationship between the carry output terminal and the input terminal of the half adder is ( ) Options: A: NAND B: OR NOT C: AND D: XOR Answer: [AND] 5. Question: Among the following logic circuits, which ones are not combinational logic circuits ( ) Options: A: Decoder B: Encoder C: Full adder D: Counter Answer: [ Counter] 6. Question: The carry signal of the serial adder is transmitted by ( ), and the carry signal of the parallel adder is transmitted by ( ). Options: A: look ahead, bit by bit B: bit by bit, look ahead C: bit by bit, bit by bit D : Ahead, ahead Answer: [bit by bit, ahead] 7. Question: The advantages and disadvantages of an n-bit adder formed by connecting n one-bit full adders in series are ( ) Option: A: Simple circuit, running speed Fast B: The circuit is complex and the running speed is fast C: The circuit is simple and the running speed is slow D: The circuit is complex and the running speed is slow Answer: [The circuit is simple and the running speed is slow] 8. Question: The four-bit binary adder 74LS283 can be used to achieve ( ) logical function. Options: A: Addition B: Subtraction C: Convert 8421BCD code to remainder 3 code D: Convert remainder 3 code to 8421BCD code Answer: [Addition; Subtraction; Convert 8421BCD code to remainder 3 code; Convert remainder 3 code to 8421BCD code] 9 , Question: Which of the following are adding machines? ( ) Options: A: 74LS183 B: 74LS138 C: 74LS283 D: 74LS148 Answer: [74LS183; 74LS283] 10. Question: The disadvantage of the serial carry adder is that the operation speed is slow, and the advantage is that the circuit structure is simple. The advantage of the carry-lookahead adder is fast operation speed, but the disadvantage is that the circuit structure is complex. ( ) Options: A: Correct B: Wrong Answer: [Correct] 11. Question: The circuit that implements the addition of two one-bit binary numbers and a carry from the low bit is called a full adder. ( ) Options: A: Correct B: Wrong Answer: [Correct] 12. Question: The adder can perform subtraction operations. ( ) Options: A: Correct B: Wrong Answer: [Correct] 13. Question: Four full adders can form a serial carry four-digit adder ( ) Options: A: Correct B: Wrong Answer: [Correct] 】 14. Question: Whether the arithmetic operation between two binary numbers is addition, subtraction, multiplication, or division, currently in digital computers, it is reduced to several steps of operation and shifting. Answer: [Addition] 15. Question: The code conversion circuit composed of an adder is as shown in the figure below. If the input signals b3, b2, b1, and b0 are 8421BCD codes, then the output terminals S3, S2, S1, and S0 are codes.

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Answer: [Remainder 3 code] 16. Question: The logical function of () can be realized by using the four-bit binary adder 74LS283. Options: A: Addition B: Subtraction C: Convert 8421BCD code to remainder 3 code D: Convert remainder 3 code to 8421BCD code Answer: [Addition; Subtraction; Convert 8421BCD code to remainder 3 code; Convert remainder 3 code to 8421BCD code] Chapter Lecture 13 Allocators and Selectors Lecture 13 Allocators and Selectors - Unit Test 1. Question: Use one of four data selectors to implement a function

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, should be used ( ).

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Options: A:D0=D1=0,D2=D3=1 B:D0=D1=1,D2=D3=0 C:D0=D2=0,D1=D3=1 D:D0=D2=1,D1 =D3=0 Answer: [D0=D2=0,D1=D3=1] 2. Question: The multi-channel data distributor can be implemented directly by ( ). Options: A: Encoder B: Multi-channel data selector C: Decoder D: Multi-bit adder Answer: [Decoder] 3. Question: To implement a multi-input, single-output logic function, you should choose (). Options: A: Data distributor B: Decoder C: Encoder D: Data selector Answer: [Data selector] 4. Question: To implement a single-input, multi-output logic function, you should choose (). Options: A: Encoder B: Decoder C: Data distributor D: Data selector Answer: [Data distributor] 5. Question: There are ( ) for 1-way to 4-way data distributors. Options: A: Four data input terminals, two selection control terminals, and one data output terminal B: Four data input terminals, one selection control terminal, and one data output terminal C: One data input terminal, two selection control terminals, Four data output terminals D: One data input terminal, one selection control terminal, four data output terminals Answer: [One data input terminal, two selection control terminals, four data output terminals] 6. Question: Known to use 8 The logic circuit formed by selecting 1 data selector 74LS151 is as shown in the figure below, then the simplest "AND or" logic function expression of output F is ( )

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Options: A:

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B:F=

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Answer: [F=

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】 7. Question: In the following circuit, appropriate auxiliary gate circuits are added, which is suitable for realizing a single output combinational logic circuit. Options: A: Binary decoder B: Data selector C: Priority encoder D: Display decoder Answer: [Binary decoder; data selector] 8. Question: Among the following logic circuits, they are combinational logic circuits Yes. Options: A: Decoder B: Encoder C: Register D: Data selector Answer: [Decoder; Encoder; Data selector] 9. Question: The function of data distributor can be realized by using data selector. Options: A: Correct B: Wrong Answer: [Wrong] 10. Question: The functions of the data selector and the data allocator are exactly opposite, and they are inverse processes of each other. Options: A: Correct B: Wrong Answer: [Correct] 11. Question: The data selector is also called a multiplexer or multiplexer circuit. This circuit is equivalent to a single-pole single-throw selector switch circuit. When there is a control When receiving a signal, the selector is in the on state and transmits data, which is equivalent to the on state of the switch. When there is no control signal, the selector is in the disconnected state and data cannot be transmitted at this time. Options: A: Correct B: Wrong Answer: [Wrong] 12. Question: The data selector is a combinational logic circuit that selects a certain data or data from ______ as the output under the action of the selection signal. Answer: [(Any one of the following answers is correct) multiple data; multi-channel data] 13. Question: Only use the 4-to-1 data selector to expand to form a 16-to-1 data selector. A 4-to-1 data selector is required. Answer: [5] 14. Question: A 32-to-1 data selector has an address input signal. Answer: [5] [Homework] Lecture 13 Allocators and Selectors Lecture 13 Allocators and Selectors - Unit Assignment 1. Question: Design a control circuit that uses three switches to control a lamp. When any switch acts (from open to closed, or from closed to open), the state of the lamp will change (from off to on, or from on to off). Assume that the switch is closed as 1, open as 0, the light on is 1, and the light off is 0; when the switch is fully open, the light goes out. It is required to create a truth table, write an expression, and implement it with a 4-to-1 data selector.

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Scoring rules: [Variable assignment and truth table total 20 points (5 points will be deducted for each mistake), expressions 10 points, circuit diagram 30 points (enable terminal 5 points, address signal 5 points, each of the four data terminals 5 points) Solution: Assume the switches are A, B, C, closed is 1, open is 0, the light is F, the light is on is 1, and the light is off is 0.

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] 2. Question: Design a 4-bit natural binary code (ABCD) odd detection circuit. When the number of 1's in the input ABCD is an odd number, the output is 1, otherwise it is 0. Use data selector 74LS151 to realize the circuit function. Scoring rules: [The truth table has a total of 20 points (5 points will be deducted for each wrong one, until all are deducted), 10 points for the reduced Vicarnot diagram, and 30 points for the circuit diagram (5 points for the enable end, 5 points for the address signal, and 20 points for the data end. If you make a mistake, 5 points will be deducted until all points are deducted)

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] [Assignment] Lecture 16 Basic RS Flip-Flop Lecture 16 Basic RS Flip-Flop - Unit Assignment 1. Question: Please draw the basic flip-flop structure composed of NAND gate and NOR gate. Scoring rules: [Composition of NAND gate The basic trigger of

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, you can answer in text, but you need to describe the clear connection components and connection methods.

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A basic flip-flop composed of a NOR gate can be answered in text, but it needs to be described to clear the connecting components and connection methods.

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】 2. Question: How to structurally change the reset and set terminals of the basic flip-flop composed of NAND gates with active low levels into the reset and set terminals with active high levels?

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Scoring rules: [You can answer in text, but you need to describe the clear connection devices and connection methods] 3. Question: How to structurally change the high-level active reset and the set end of a basic flip-flop composed of a NOR gate to a low level Valid reset and set terminals

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Scoring rules: [You can answer in text, but you need to describe the clear connection components and connection methods] Lecture 17 Flip-flop circuit structure and action characteristics Lecture 17 Flip-flop circuit structure and action characteristics - Unit test 1. Question: Only those with "0" " and the trigger of the "1" function is ( ). Options: A: Basic RS flip-flop B: Clocked RS flip-flop C: D flip-flop D: JK flip-flop Answer: [D flip-flop] 2. Question: The basic RS flip-flop composed of NAND gates does not allow input The variable combination R S ⋅ is ( ) Options: A:00 B:01 C:10 D:11 Answer: [00] 3. Question: The flip-flop is composed of a gate circuit, but it has different gate circuit functions. Its main feature is that it has ( ) Options: A: Flip function B: Hold function C: Memory function D: Set 0 and set 1 function Answer: [Memory function] 4. Question: Which of the following flip-flops has constraints ( ) Option: A: Basic RS flip-flop B: Edge D flip-flop C: Master-slave JK flip-flop D: T flip-flop Answer: [Basic RS flip-flop] 5. Question: The state transition diagram of the flip-flop is as follows, then it is: ( )

Options: A: T flip-flop B: SR flip-flop C: JK flip-flop D: D flip-flop Answer: [D flip-flop] 6. Question: If a master-slave flip-flop is used, the triggering method is ( ) Option: A : Level trigger mode B: Pulse trigger mode C: Edge trigger mode D: Unsure Answer: [Pulse trigger mode] 7. Question: Assume that the initial states of all flip-flops in the picture are 0, find out where the trigger in the picture is Under the action of the clock signal, the output voltage waveform is always 0: ( ) Figure. Options: A:

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Answer: 【

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] 8. Question: "Somersault" refers to ( ) Options: A: When the clock signal acts, the output state of the flip-flop flips multiple times with the change of the input signal B: The output state of the flip-flop depends on the input signal C: Trigger The output state of the flip-flop depends on the clock signal and the input signal. D: always causes the output to change state. Answer: [When the clock signal acts, the output state of the flip-flop flips multiple times with the change of the input signal] 9. Question: J=K =1, the clock input frequency of the JK flip-flop is 120Hz, and the Q output is ( ) Options: A: Maintain high level B: Maintain low level C: Square wave with frequency of 60Hz D: Square wave with frequency of 240Hz Wave answer: [Square wave with a frequency of 60Hz] 10. Question: 6. The purpose of introducing a clock pulse to the flip-flop is ( ) Options: A: Change the output state to high level B: Change the output state C: The moment when the output state is changed Controlled by the clock pulse D: Maintain the stability of the output state Answer: [The moment when the output state is changed is controlled by the clock pulse] 11. Question: The JK flip-flop is under the action of CP. If J=K=0, the flip-flop is set 0 (i.e. reset). Options: A: Correct B: Wrong Answer: [Wrong] 12. Question: According to the triggering method, it can be divided into: level trigger, pulse trigger, ( ) trigger. Answer: [Edge] Lecture 16 Basic RS Flip-Flop Lecture 16 Basic RS Flip-Flop-Unit Test 1. Question: For flip-flops and combinational logic circuits, the following ( ) statements are correct. Options: A: Both have memory capabilities B: Neither have memory capabilities C: Only combinational logic circuits have memory capabilities D: Only flip-flops have memory capabilities Answer: [Only flip-flops have memory capabilities] 2. Question: Use It is a basic RS flip-flop composed of NAND gate and the input signal is active at high level. When the input signal S= 0 and R= 1, its logic function is ( ). Options: A: Set to 1 B: Set to 0 C: Keep D : Uncertain Answer: [Set to 0] 3. Question: Among the following flip-flops, which input signal directly controls the output state ( ) Options: A: Basic RS flip-flop B: Clocked RS flip-flop C: Master-slave JK flip-flop D :Maintain blocked D flip-flop Answer: [Basic RS flip-flop] 4. Question: In the RS flip-flop where the input signal is high-level active, the input is not allowed ( ) Option: A: RS=00 B: RS=01 C :RS=10 D:RS=11 Answer: [RS=11] 5. Question: The flip-flop has two stable states, one is the current state and the other is the secondary state. Options: A: Correct B: Wrong Answer: [Wrong] 6. Question: The flip-flop has two stable states. Under the action of external input signals, it can change from one stable state to another. Options: A: Correct B: Wrong Answer: [Correct] 7. Question: Flip-flops with the same logic function must have the same circuit structure. Options: A: Correct B: Wrong Answer: [Wrong] 8. Question: The flip-flop has ( ) stable states. Answer: [(Any one of the following answers is correct) 2; two; both] 9. Question: In basic In the RS flip-flop, the input terminal DR or /DR can make the flip-flop in ( ) state. Answer: [(Choose any one of the following answers is correct) clear; reset] 10. Question: In the basic RS flip-flop, the input terminal DS or /DS can make the flip-flop in ( ) state. Answer: [(Any one of the following answers is correct) set the number; set 1] [Assignment] Lecture 17 Flip-flop Circuit Structure and Action Characteristics Lecture 17 Flip-Flop Circuit Structure and Action Characteristics - Unit Assignment 1. Question: What is the one-time change phenomenon of the master-slave flip-flop? Scoring rules: [The so-called one-time flipping phenomenon of the master-slave JK flip-flop is that during the CP=1 period, no matter how many times the input signals J and K change, the master flip-flop can and can only flip once. ] 2. Question: What are the requirements for trigger pulses of master-slave flip-flops and maintenance-blocking flip-flops? Scoring rules: [Master-slave JK flip-flop requires the JK signal to remain unchanged when CP=1. However, due to a change problem, the master-slave JK flip-flop can receive interference signals and memorize the interference, causing error actions. This is undesirable. The only solution is to reduce the time of CP=1, but this It is possible to cause instability in status reversal. (6 points) Edge triggers only consider the rising edge or falling edge of the trigger pulse (4 points)] Lecture 18: Description and application of the logical function of the flip-flop Lecture 18: Description and application of the logical function of the flip-flop - Unit test 1. Questions : To change the state of the JK flip-flop from 0 to 1, the added excitation signal JK should be ( ) Options: A: 0× B: 1× C: × 1 D: × 0 Answer: [1×] 2. Question : For D flip-flop, if the excitation signal D=1 added before the CP pulse arrives, the state of the flip-flop can be changed ( ). Options: A: From 0 to 0 B: From × to 0 C: From 1 to 0 D: Change from × to 1 Answer: [Change from When changing from "1" to "0", the status of the trigger changes to ( ). Options: A: "0" → "1" B: "1" → "0" C: unchanged D: indefinite Answer: ["0" → "1"] 4. Question: For T flip-flop, when T= ( ), the flip-flop is in the hold state. Options: A: 0 B: 1 C: 0 or 1 D: None of the above Answer: [0 ] 5. Question: For JK flip-flop, if J=K, the logical function of ( ) flip-flop can be completed. Options: A:RS B:D C:T D:T' Answer: [T] 6. Question: To make the secondary state of the JK flip-flop under the action of the clock opposite to the current state, the value of the JK terminal should be ( ) Option: A :00 B:01 C:10 D:11 Answer: [11] 7. Question: The reversal condition of the flip-flop is determined by the trigger input and the clock pulse. ( ) Options: A: Correct B: Wrong Answer: [Correct] 8. Question: D flip-flops are only valid on the rising edge of the clock pulse. Options: A: Correct B: Wrong Answer: [Wrong] 9. Question: Synchronous RS flip-flop is used in switch debounce. Options: A: Correct B: Wrong Answer: [Wrong] 10. Question: Synchronous flip-flops have somersault phenomenon, while edge triggers and master-slave flip-flops overcome somersaults. Options: A: Correct B: Wrong Answer: [Correct] 11. Question: The D flip-flop shown in the picture is a rising edge flip-flop.

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Options: A: Correct B: Wrong Answer: [Wrong] [Assignment] Lecture 18: Logical Function Description and Application of Flip-Flop Lecture 18: Logic Function Description and Application of Flip-Flop - Unit Assignment 1. Question: Known master-slave JK The waveforms of flip-flops J and K are as shown in the figure. Draw the waveform diagram of the output Q (assume the initial state is 0)

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Judging rules: 【

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Calculate the score based on the clock cycles starting from the 6 falling edges, 2 points each] 2. Question: Given the input signal waveform of the synchronous D flip-flop, draw the output Q terminal signal waveform.

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Judging rules: 【

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Check the output status according to each cycle starting from the rising edge of the 6 clocks, 2 points each] Lecture 19 Characteristics and description methods of sequential logic circuits Lecture 19 Characteristics and description methods of sequential logic circuits - Unit test 1. Question: Timing Logic circuits are usually ( ) essential. Options: A: Memory B: Gate circuit C: Combinational logic circuit D: AND, OR, NOT logic gate circuit Answer: [Memory] 2. Question: The storage circuit that can be used as a sequential logic circuit is () Option: A: Flip-flop B: Adder C: Comparator D: Decoder Answer: [Flip-flop] 3. Question: The description method of sequential logic circuit is () Options: A: Logic expression B: State diagram C: State table D: State Equation E: Sequence diagram answer: [Logical expression; state diagram; state table; state equation] 4. Question: The equation description of the sequential circuit includes () Options: A: Output equation B: State equation C: Driving equation D: Algebra Answer to the equation: [Output equation; State equation; Driving equation] 5. Question: Sequential logic circuits must have feedback branches Options: A: Correct B: Wrong Answer: [Correct] 6. Question: Combinational logic circuits with feedback branches It must be a sequential logic circuit. Options: A: Correct B: Wrong Answer: [Wrong] 7. Question: The synchronous sequential circuit must be a Moore type circuit. Options: A: Correct B: Wrong Answer: [Wrong] 8. Question : Any method of describing sequential logic circuits can be converted to each other. Options: A: Correct B: Wrong Answer: [Correct] 9. Question: The storage circuit of a sequential logic circuit usually consists of () Answer: [(Answer below (Any one is correct) Flip-flop; flip-flop group] 10. Question: Sequential logic circuit realizes () function through memory. Answer: [Memory] [Homework] Lecture 21 Design of Sequential Logic Circuit Lecture 21 Sequential Logic Circuit Design - Unit Assignment 1. Question: Use JK flip-flop to complete the design of "111" sequence detector. There must be a design process that provides state simplification, state assignment, excitation functions and output functions, self-starting and logic diagrams. Scoring rules: [State simplification (10 points), state allocation (10 points), incentive function and output function (10 points), self-starting (10 points) and logic diagram (10 points). For each sub-item, 5 points will be deducted for one mistake and no points for two mistakes.

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】 2. Question: Use JK flip-flop to design a quinary synchronous counter. See the attachment for the Q2Q1Q0 state transition relationship. There must be a design process that provides state tables, state assignments, excitation functions and output functions, self-starting and logic diagrams. Scoring rules: [State table (10 points), state equation (10 points), excitation function (including modified design) (10 points), self-starting (10 points) and logic diagram (10 points). For each sub-item, 5 points will be deducted for one mistake and no points for two mistakes.

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】 [Assignment] Lecture 19 Characteristics and description methods of sequential logic circuits Lecture 19 Characteristics and description methods of sequential logic circuits - Unit homework 1. Question: Given the state diagram of the sequential logic circuit, draw its state table and timing respectively. picture. Scoring rules: [50 points for correctly completing the status table and 50 points for the timing diagram. 10 points will be deducted for every mistake, until the full 50 points are deducted.

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] [Assignment] Lecture 20 Analysis of Sequential Logic Circuits Lecture 20 Analysis of Sequential Logic Circuits - Unit Assignment 1. Question: Analysis of synchronous sequential logic circuits requires driving equations, state equations, state diagrams, timing diagrams and logic function scores Rules: [Asynchronous sequential logic circuit analysis, driving equation (10 points), state equation (10 points), state diagram (10 points), timing diagram (10 points) and logic function (10 points). Logic Function: This circuit is a synchronous modulo 4 reversible counter. X is the addition/subtraction control signal, and Z is the borrow output.

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] 2. Question: Analysis of asynchronous sequential logic circuits requires clock equation, state equation, state table, state diagram and logic function scoring rules: [clock equation (10 points), state equation (10 points), state table (10 points) ), state diagram (10 points) and logic function (10 points). No points will be given if there is no process. If you make one mistake in each item, 5 points will be deducted. If you make two mistakes, no points will be awarded.

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] Lecture 21 Design of Sequential Logic Circuits Lecture 21 Design of Sequential Logic Circuits - Unit Test 1. Question: According to the difference in the () signals received by each flip-flop of a sequential logic circuit, it is divided into synchronous sequential logic circuits and asynchronous sequential logic circuits. Options: A: Clock pulse control B: Edge signal C: High level D: Pulse signal Answer: [Clock pulse control] 2. Question: When there is only a storage circuit output in a sequential logic circuit, the circuit type is usually called ( ) type sequential logic circuit. Options: A: Mile B: Mohr type C: Synchronous sequential circuit D: Asynchronous sequential circuit Answer: [Moiré type] 3. Question: The three major equations are methods of describing sequential logic circuits. The three major equations description method refers to () Options: A: Algebraic equation B: Driving equation C: State equation D: Output equation Answer: [Driving equation; State equation; Output equation] 4. Question: The three major diagrams are also methods of describing sequential logic circuits. The three major diagrams The description method refers to () Options: A: State table B: State diagram C: Logic diagram D: Truth table Answer: [State table; State diagram; Logic diagram] 5. Question: State coding is a decimal code to represent the number of states Options: A: Correct B: Wrong Answer: [Correct] 6. Question: State simplification is to eliminate redundant states and obtain the minimized state table options: A: Correct B: Wrong Answer: [Correct] 7. Question: If a certain sequential logic circuit cannot start automatically, the circuit state can be set to a valid cycle state through the preset number. Options: A: Correct B: Wrong Answer: [Correct] 8. Question: If a certain sequential logic circuit cannot start automatically, it can be solved by modifying the logic design. Options: A: Correct B: Wrong Answer: [Correct] 9. Question: Synchronous sequential logic circuit design and () are mutually reversible processes. Answer: [Synchronous sequential logic circuit analysis] 10. Question: If a sequential logic circuit has 8 states , then at least () bits of binary coding are required to represent the answer: [3] Lecture 20 Analysis of Sequential Logic Circuits Lecture 20 Analysis of Sequential Logic Circuits - Unit Test 1. Question: The difference between sequential logic circuits and combinational logic circuits, mainly In () Options: A: Whether there is a gate circuit B: Whether there is a clock C: Whether there is a storage circuit D: Whether there is a decoder Answer: [Whether there is a storage circuit] 2. Question: What is the difference between synchronous sequential circuits and asynchronous sequential circuits? In () options: A: Whether there is a feedback branch B: Whether there is a flip-flop C: Whether there is an external clock D: Whether the external clock signal acts on the clock end of the flip-flop at the same time Answer: [Whether the external clock signal acts on the flip-flop at the same time clock end] 3. Question: The difference between the analysis method of asynchronous sequential circuit and the analysis method of asynchronous sequential circuit is () Options: A: Consider the output equation of each flip-flop B: Consider the state equation of each flip-flop C: Consider Whether each flip-flop is an edge flip-flop D: Consider the clock equation of each flip-flop Answer: [Consider the clock equation of each flip-flop] 4. Question: The essential difference between sequential logic circuits and combinational logic circuits is () Options: A: Memory B: Gate circuit C: Flip-flop D: Feedback branch Answer: [Memory; Flip-flop; Feedback branch] 5. Question: Compared with asynchronous sequential circuits, the essential difference between synchronous sequential circuits and asynchronous sequential circuits is () Option: A :Flip-flop B: The external clock signal acts on the clock terminals of all flip-flops C: Logic gate D: The changes in the state of all flip-flops occur simultaneously Answer: [The external clock signal acts on the clock terminals of all flip-flops; all flip-flops The changes in state are simultaneous] 6. Question: Sequential logic circuits can be divided into synchronous sequential logic circuits and asynchronous sequential logic circuits according to their structures. Options: A: Correct B: Wrong Answer: [Wrong] 7. Question: In sequential logic circuits The basic unit circuit is a flip-flop option: A: Correct B: Wrong Answer: [Correct] 8. Question: The analysis of sequential logic circuits is to analyze the logical function options of the circuit based on a given sequential logic circuit: A: Correct B: Wrong answer: [Correct] 9. Question: Sequential logic circuits mainly include combinational circuits and (). Answer: [(choose any one of the following answers is correct) flip-flop; memory] 10. Question: Asynchronous sequential circuit analysis method Compared with the synchronous sequential logic circuit analysis method, each flip-flop () equation needs to be considered. Answer: [Clock] [Assignment] Lecture 23 Registers and Shift Registers Section 23 Registers and Shift Registers - Unit Assignment 1. Question: Try a negative edge JK flip-flop and an "AND-OR-NOT" gate to form a four-digit digital parallel register and a four-digit digital serial input right shift register (implemented in the same circuit, you can add a control terminal, and have solution process). Scoring rules: [Shift register parallel storage data function (10 points, deduct 5 points for 1 mistake, no points for 2 mistakes), right shift function (20 points, deduct 5 points for 1 mistake, no points for 2 mistakes) ), design analysis process (20 points, 10 points for explaining the parallel function, 10 points for the right shift function).

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] 2. Question: As shown in the figure, it is a circuit diagram for realizing serial addition. The summand 11011 and the addend 10111 have been stored in two five-bit summand and addend shift registers respectively. Try to analyze and draw the output waveforms of the full adder output Si terminal, the carry flip-flop Q terminal and the left first register unit in the sum shift register under the action of six clock pulses (one-to-one correspondence is required in time). Scoring rules: [Full adder output Si terminal waveform (15 points, deduct 5 points for 1 mistake, no points for 2 mistakes), carry flip-flop Q terminal waveform (15 points, deduct 5 points for 1 mistake, 2 mistakes No points will be given) and the output waveform of the first register unit on the left in the sum shift register (20 points, 5 points will be deducted for 1 mistake, and no points will be given for 2 mistakes).

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] [Homework] Lecture 22 Counters Lecture 22 Counters - Unit Assignment 1. Question: Use 74LS163 to design a modulo 6 counter using the reset method, the set 0 method, the set maximum number method and the CO set minimum number method, and list them Valid count status table. Scoring rules: [Reset method (10 points), Set 0 method (10 points), Set maximum number method (10 points), and CO Set minimum number method (10 points) (One mistake in each of the above sub-items will deduct points, and 2 mistakes will be made No points will be given for any error), effective counting status table (20 points, 5 points for each sub-item, 3 points will be deducted for 1 error in each sub-item, and no points will be awarded for 2 errors).

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] 2. Question: Use D flip-flop to design a modulo-seven synchronous adding counter. Its Q2Q1Q0 status changes from 000-001-010-011-100-101-110. Requires state tables, driving equations, state equations, self-starting checks, and logic diagrams. Scoring rules: [State table (10 points), driving equation (10 points), self-starting check (10 points), logic diagram (10 points). For each sub-item, 2 points will be deducted for 1 mistake, and no points will be given for 2 mistakes.

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] Lecture 22 Counter Lecture 22 Counter-Unit Test 1. Question: An N-bit binary counter requires () flip-flops. Options: A:N B:N-1 C:

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Answer: [N] 2. Question: The modulus of an N-bit binary counter is (). Options: A:

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C:N D:

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Answer: 【

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] 3. Question: The counter is divided into () according to the increasing and decreasing trend of the count. Options: A: Up counter B: Down counter C: Reversible counter D: Synchronous counter E: Asynchronous counter Answer: [Up counter; Down counter; Reversible counter] 4. Question: The integrated asynchronous binary counter 74293 has 4 internal flip-flops. , can implement () base counter. Options: A: Binary counter B: Octal counter C: Hexadecimal counter D: Binary counter Answer: [Binary counter; Octal counter; Hexadecimal counter] 5. Question: What is the difference between synchronous decimal counter and asynchronous decimal counter? In the former case, flip-flop state flips occur simultaneously. Options: A: Correct B: Wrong Answer: [Correct] 6. Question: The synchronous clearing terminal does not require effective pulse coordination when the clearing terminal is valid. Options: A: Correct B: Wrong Answer: [Wrong] 7. Question: It is required that the module of the arbitrary base counter designed is smaller than the module of the counter of the counter chip used. Options: A: Correct B: Wrong Answer: [Wrong] 8. Question: The integrated synchronous decimal counter 74160 must have self-starting capability. Options: A: Correct B: Wrong Answer: [Correct] 9. Question: A 4-bit binary counter implements a () base counter. Answer: [16] 10. Question: The 1KHz pulse signal is input to a decimal counter, and a pulse signal with a frequency of () Hz is obtained. Answer: [10] Lecture 23 Registers and Shift Registers Section 23 Registers and Shift Registers - Unit Test 1. Question: When a 4-bit shift register is used to form a ring counter, there are () valid status options: A: 2 B:4 C:8 D:16 Answer: [4] 2. Question: When using a 4-bit shift register to form a twisted ring counter, there are () valid status options: A:4 B:6 C:8 D:16 Answer: [8] 3. Question: 74LS194 has the following functions () Options: A: Left shift B: Right shift C: Parallel reset D: Data clear E: Data retention Answer: [Left shift; Right shift; Parallel reset Number; data cleared; data retained] 4. Question: The following devices belonging to sequential logic circuits are (). Options: A: Flip-flop B: Shift register C: Adder D: Decoder Answer: [Flip-flop; shift register] 5. Question: Both 74194 and 74LS194 have () input and () output mode options: A :serial serial B:serial parallel C:parallel serial D:parallel parallel Answer: [serial serial; serial parallel; parallel serial; parallel parallel] 6. Question: The 8421BCD code can be formed using a shift register Counter options: A: Correct B: Wrong Answer: [Wrong] 7. Question: Implementing the 74LS194 shift register clearing function requires the cooperation of an external clock. Options: A: Correct B: Wrong Answer: [Wrong] 8. Question: The shift register can realize the data serial-to-parallel conversion function. Options: A: Correct B: Wrong Answer: [Correct] 9. Question: The shift register can realize the counting function. Options: A: Correct B: Wrong Answer: [Correct] 10. Question: A shift register requires a clock to implement bidirectional shifting and parallel setting. Options: A: Correct B: Wrong Answer: [Correct] 11. Question: Shift The gate option is required to realize bidirectional shifting and parallel setting of registers: A: Correct B: Wrong Answer: [Correct] 12. Question: The shift register has digital register and () functions. Answer: [Shift] 13. Question: The digital register has the data () function. Answer: [Storage] Lecture 24 Other Common Sequential Logic Circuits and Competition-Dangerous Phenomenon Section 24 Other Common Sequential Logic Circuits and Competition-Dangerous Phenomenon - Unit Test 1. Question: The sequential pulse generator converts the input pulse sequence into ()Signal. Options: A: Pulse B: Continuous pulse signal C: A group of pulses that appear continuously D: A group of pulses that appear sequentially in time Answer: [A group of pulses that appear sequentially in time] 2. Question: In a shift register On the basis of adding () ready-made shift register type sequence signal generator. Options: A: Combination circuit B: Flip-flop C: Feedback network D: Logic gate Answer: [Feedback network] 3. Question: The sequential pulse generator is called (). Options: A: Shift register group B: Beat pulse generator C: Pulse distributor D: Flip-flop group Answer: [Tick pulse generator; pulse distributor] 4. Question: Sequential pulse generator usually consists of () circuit . Options: A: Comparator B: Decoder C: Data selector D: Counter Answer: [Decoder; Counter] 5. Question: A circuit that can generate sequence signals is called a sequence signal generator. Options: A: Correct B: Wrong Answer: [Wrong] 6. Question: The length of the sequence signal depends on how many bits there are in the sequence signal. Options: A: Correct B: Wrong Answer: [Correct] 7. Question: Sequence signal generators are divided into shift register type and counter type according to their structure. Options: A: Correct B: Wrong Answer: [Correct] 8. Question: It is impossible for a counter-type sequential pulse generator to produce a competition risk. Options: A: Correct B: Wrong Answer: [Wrong] 9. Question: A circuit that can generate sequence signals cyclically is called (). Answer: [Sequence signal generator] 10. Question: To design a set of 0010 1110, 0010 1110, —, sequence signal generator, the number of digits required in the register is (). Answer: [3] [Assignment] Lecture 24 Other common sequential logic circuits and competition-risk phenomena Lecture 24 Other common sequential logic circuits and competition-risk phenomena-Unit homework 1. Question: Design integrated counter 74LS163 and integrated 3-wire -8-line decoder 74LS138 constitutes an 8-output sequential pulse generator (requires drawing of logic circuit and principle analysis). Scoring rules: [Logic circuit diagram (25 points, 5 points will be deducted for every mistake, until the deduction is completed), principle analysis (can also be reflected in the timing diagram) (25 points, 5 points will be deducted for every mistake, until the deduction is completed). As long as the logic diagram can realize the function, points will be awarded as appropriate for the principle analysis.

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] 2. Question: Design the output sequence of the sequence signal generator 0011 1001, 0011 1001, using counter 74293 and 8-to-1 data selector to implement it. Scoring rules: [Counter (25 points), data selector design (25 points), points will be awarded appropriately based on completion.

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] Lecture 25 555 time base circuit and its application Lecture 25 555 time base circuit and its application - unit test 1. Question: Monostable circuit can be used in which of the following situations. Options: A: Oscillator B: Adder C: Timing circuit D: Shift register Answer: [Timing circuit] 2. Question: When the integrated 555 circuit is not used at the CO terminal, the reference voltage of the comparator Cl is, the reference of C2 The voltage is. A.2/3Vcc B.1/3Vcc C.Vcc D. 1/2Vcc Options: A:A,B B:C,D C:B,C D:A,C Answer: [A,B] 3. Question: Integration 555 When the circuit adds control voltage Vco to the control voltage terminal CO, the reference voltages of C1 and C2 will become respectively. A.2/3Vco B.1/3Vco C.Vco D.1/2Vco Options: A:A,D B:A,B C:C,D D:B,C Answer: [C,D] 4. Question: Schmidt Special flip-flops are type circuits. Options: A: Latch B: Level trigger C: Edge trigger D: Pulse trigger Answer: [Level trigger] 5. Question: When the Schmitt trigger is used for shaping, the amplitude of the input signal should be . Options: A: Equal to VT+ B: Less than VT- C: Greater than VT+ D: Equal to VT- Answer: [Greater than VT+] 6. Question: The flip of a monostable circuit from a stable state to a transient stable state depends on the flip from a transient stable state to steady state depends. A.Pulse width B.R and C C.Threshold voltage D.Input pulse signal options: A:A,B B:B,C C:B,D D:D,B Answer: [D,B] 7. Question: It is monostable Circuit output pulse width. Options: A: 0.7 times the transient steady state time B: Temporary stable state time C: Steady state time D: 0.7 times the steady state time Answer: [Transient stable state time] 8. Question: Monostable trigger and multiharmonic The transient steady-state time in the oscillator is proportional to . Options: A: Pulse width B: R and C C: Threshold voltage D: Input pulse signal Answer: [R and C] 9. Question: To make the oscillator composed of integrated 555 circuit stop oscillating, it should be handled as follows. Options: A: Reset terminal is connected to low level B: Reset terminal is connected to high level C: CO terminal is connected to high level D: CO terminal is connected to low level Answer: [Reset terminal is connected to low level] 10. Question: 555 timing The multivibrator composed of oscillators is shown in the figure below, and its oscillation period is approximately.

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Options: A:0.7(RA+RB)C B:0.7(RA+2RB)C C:(RA+2RB)C D:1.2(RA+RB)C Answer: [0.7(RA+2RB)C] 11. Question: 555 The multivibrator composed of a timer is shown in the figure below. Its charging time constant and discharging time constant are.

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Options: A: (RA+RB)C, RAC B:RAC, RBC C:RBC, RAC D:RAC, (RA+RB)C Answer: [RAC, RBC] 12. Question: Name of the circuit shown in the figure below Yes; the width of the trigger pulse meets the requirements.

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Options: A: Monostable trigger, the width of the trigger pulse is less than the transient stable time B: Monostable trigger, the width of the trigger pulse is greater than the transient time C: Multivibrator, the width of the trigger pulse is greater than the transient time State time D: Schmitt trigger, the width of the trigger pulse is equal to the transient stable state time Answer: [Monostable trigger, the width of the trigger pulse is less than the transient stable state time] 13. Question: Schmitt composed of 555 time base circuit Special trigger (the 5-pin control terminal is connected to ground through a capacitor), when the power supply voltage is 15V, its hysteresis voltage is ( ). Options: A:5V B:10V C:15V D:25V Answer: [5V] 14. Question: In digital systems, it is commonly used to convert slowly changing input signals into rectangular pulse signals. Options: A: Monostable trigger B: Multivibrator C: Schmitt trigger D: Astable trigger Answer: [Schmitt trigger] 15. Question: The main function of Schmitt trigger is , , wait. Options: A: Improve drive load capacity B: Amplitude identification C: Signal shaping D: Waveform transformation Answer: [Amplitude identification; Signal shaping; Waveform transformation] 16. Question: The circuit structure of a multivibrator can be summarized into two parts: and . Options: A: Schmitt trigger B: Switching device C: Monostable trigger D: Positive feedback delay link Answer: [Switching device; Positive feedback delay link] 17. Question: The integrated 555 circuit is set at the output front end The main reason for using an inverter is. Options: A: Keep the discharge terminal level consistent with the output terminal level B: Improve the drive load capacity C: Increase the high level D: Reduce the low level Answer: [The discharge terminal level should be consistent with the output terminal level; improve the drive load capacity ] [Assignment] Lecture 25 555 time base circuit and its application Lecture 25 555 time base circuit and its application - unit assignment 1. Question: A simple electronic doorbell circuit composed of a 555 timer is shown in the figure. Analyze the circuit shown in the figure. , (1) Explain the name of the circuit composed of 555(1) and 555(2) in the figure. (2) If the speaker is required to continue to sound at a frequency of 1.2kHz for 10 seconds after the switch s is pressed, try to determine the resistance values of R1 and R2 on the way.

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Scoring rules: [ (1) (1) is a monostable trigger circuit; (2) is a multivibrator circuit, 10 points each. (2) The speaker continues to sound for 10 seconds, indicating that the transient stable state time of the monostable trigger circuit is 10 seconds. Formula

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5 points calculated

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10 points The speaker emits sound at a frequency of 1.2kHz. The oscillation frequency formula of the multivibrator is: 5 points

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Calculate R2=0.61KΩ, 10 points] 2. Question: A simple touch switch circuit composed of 555. When the hand touches the metal sheet, the light-emitting diode lights up. After a period of time, the light-emitting diode automatically goes out. Please explain: (1) The name of the circuit composed of 555; (2) How long does the light-emitting diode stay on.

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Scoring rules: [ (1) Monostable trigger circuit; 20 points (2)

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30 points] [Assignment] Lecture 31 CPLD Lecture 31 CPLD-Unit Assignment 1. Question: Assignment 1: Compare the differences in structure and performance between FPGA and CPLD systems based on lookup tables? Scoring rules: [Performance: Logic circuits in In the small and medium-sized range, CPLD is cheaper and can be used directly in the system. For large-scale logic circuit design, FPGA is often used. Because in terms of logical scale, FPGA covers large and medium-sized ranges. For large-scale logic circuit design, FPGA is often used. Because in terms of logical scale, FPGA covers large and medium-sized ranges. ] [Assignment] Lecture 30 PLD Basics Lecture 30 PLD Basics - Unit Assignment 1. Question: PLD types and their characteristics Scoring rules: [Type: EPROM/PAL/PLA/GAL Characteristics: From the perspective of arrays and or arrays Just say it] Lecture 31 CPLD Lecture 31 CPLD-Unit Test 1. Question: IP core plays a very important role in EDA technology and development. IP refers to ( ). Options: A: Intellectual property B: Internet protocol C: Network address D: None Answer: [Intellectual property] 2. Question: Large-scale programmable devices mainly include FPGA and CPLD. The following describes the structure and working principle of FPGA. , the correct one is ( ). Options: A: FPGA is a programmable logic device based on product term structure; B: FPGA is a full name of complex programmable logic device; C: SRAM-based FPGA device must be configured once after each power-on; D: In Among the devices produced by Altera, the MAX7000 series belongs to the FPGA structure. Answer: [SRAM-based FPGA devices must be configured once after each power-on;] 3. Question: Electronic system design optimization mainly considers improving resource utilization and reducing power consumption (i.e. area optimization) and increasing operating speed (i.e. Speed optimization), the following methods ( ) do not belong to area optimization. Options: A: Pipeline design B: Resource sharing C: Logic optimization D: Serialization Answer: [Pipeline design] 4. Question: Large-scale programmable devices mainly include CPLD and FPGA. The following is the structure and working principle of FPGA In the description, the correct one is ( ) option: A: FPGA stands for complex programmable logic device B: FPGA is a programmable logic device based on product term structure. C: SRAM-based FPGA devices must be configured every time they are powered on. D: Among the devices produced by Altera, the MAX7000 series belongs to the FPGA structure. Answer: [SRAM-based FPGA devices must be configured once after each power-on. ] 5. Question: Large-scale programmable devices mainly include CPLD and FPGA. Among them, CPLD realizes its logic function through ( ). Options: A: Programmable product term logic; B: Lookup table (LUT) C: Input buffer D: Output buffer Answer: [Programmable product term logic;] 6. Question: Currently, FPGAs produced by Xilinx mainly use ROM configuration memory structure. Options: A: Correct B: Wrong Answer: [Wrong] Analysis: [SRAM] 7. Question: EDA in the field of modern electronic system design adopts a bottom-up design method. Options: A: Correct B: Wrong Answer: [Wrong] Analysis: [Top-down] 8. Question: The FPGA/CPLD design process is: schematic/HDL text input → functional simulation → synthesis → adaptation → timing simulation → Programming download→Hardware test. Options: A: Correct B: Wrong Answer: [Correct] 9. Question: The future development trend of integrated circuit technology is to integrate the entire system on one chip. This chip is called CPLD or FPGA. Options: A: Correct B: Wrong Answer: [Wrong] Analysis: [System on Chip SOC] 10. Question: CPLD evolved from the structure of a simple PLD. Options: A: Correct B: Wrong Answer: [Correct] 11. Question: The core part of FPGA is the logic cell array LCA, which is composed of an internal logic block matrix and surrounding I/O interface modules. Options: A: Correct B: Wrong Answer: [Correct] Lecture 30 PLD Basics Lecture 30 PLD Basics - Unit Test 1. Question: Large-scale programmable devices mainly include FPGA and CPLD. The following describes the structure and working principle of FPGA In the description, the correct one is ( ). Options: A: FPGA is a programmable logic device based on product term structure; B: FPGA is a full name of complex programmable logic device; C: SRAM-based FPGA device must be configured once after each power-on; D: In Among the devices produced by Altera, the MAX7000 series belongs to the FPGA structure. Answer: [SRAM-based FPGA devices must be configured once after each power-on;] 2. Question: Which of the following EDA software does not have logic synthesis function: ( ). Options: A:ISE B:ModelSim C:Quartus II D:Synplify Answer: [ModelSim] 3. Question: Large-scale programmable devices mainly include FPGA and CPLD. Among the following descriptions of the structure and working principle of CPLD, which one is correct? yes( ). Options: A: CPLD is a programmable logic device based on a lookup table structure; B: CPLD is the English abbreviation of field programmable logic device; C: Early CPLD was expanded from the structure of GAL; D: Produced by Xilinx Among the devices, the XC9500 series has a CPLD structure; Answer: [Among the devices produced by Xilinx, the XC9500 series has a CPLD structure;] 4. Question: IP core plays a very important role in EDA technology and development; VHDL, etc. are provided. The hardware description language describes the function block, but does not involve the IP core of the specific circuit that implements the function block ( ). Options: A: Thin IP B: Solid IP C: Fat IP D: None Answer: [None] 5. Question: What structure is the programmability of CPLD mainly based on ( ) Options: A: Lookup table (LUT) B: PAL programmable C: ROM programmable D: AND-OR array programmable Answer: [AND-OR array programmable] 6. Question: The programmable structure that FPGA programmable logic is based on is based on ( ). Options: A: LUT structure B: Product term structure C: PLD D: None of them are correct Answer: [LUT structure] 7. Question: The programmable structure that CPLD programmable logic is based on is based on ( ). Options: A: LUT structure B: Product term structure C: PLD D: None of them are correct Answer: [Product term structure] 8. Question: Express the designed system in a certain form according to the requirements of EDA development software and send it to the computer The process is called ( ) Options: A: Design input B: Design output C: Simulation D: Comprehensive answer: [Design input] 9. Question: After the design input is completed, the file should be processed ( ) immediately. Options: A: Compile B: Edit C: Functional simulation D: Timing simulation Answer: [Compile] 10. Question: The most commonly used design method for digital system design based on hardware description language is called ( ) design method. Options: A: Bottom-up B: Top-down C: Building block D: Top-level Answer: [Top-down] 11. Question: In EDA tools, software that can complete layout and routing on target system devices is called translater. Options: A: Correct B: Wrong Answer: [Wrong] Analysis: [Adapter] 12. Question: After the design input is completed, the file should be synthesized immediately. Options: A: Correct B: Wrong Answer: [Error] Analysis: [Compile] 13. Question: The most commonly used design method for digital system design based on hardware description language is called top-down design method. Options: A: Correct B: Wrong Answer: [Correct] 14. Question: The process of converting a hardware description language into a hardware circuit is called compilation. Options: A: Correct B: Wrong Answer: [Wrong] Analysis: [Comprehensive] 15. Question: IP core plays a very important role in EDA technology and development. IP provided in HDL is called soft IP. Options: A: Correct B: Wrong Answer:[Correct] Lecture 32 Preliminary HDL Design Lecture 32 Preliminary HDL Design - Unit Test 1. Question: What structure is the programmability of CPLD mainly based on ( ). Options: A: Lookup table (LUT) B: PAL programmable C: ROM programmable D: AND or array programmable Answer: [AND or array programmable] 2. Question: The programmable structure of FPGA programmable logic is based on ( ). Options: A: LUT structure B: Product term structure C: PLD D: None of them are correct Answer: [LUT structure] 3. Question: The programmable structure that CPLD programmable logic is based on is based on ( ). Options: A: LUT structure B: Product term structure C: PLD D: None of them are correct Answer: [Product term structure] 4. Question: Which of the following operators has the highest priority ( ). Options: A:! B:+ C:& D:{} Answer: [! 】 5. Question: Which of the following FPGA/CPLD design processes is correct ( ) Option: A: Schematic/HDL text input->Functional simulation->Synthesis->Adaptation->Programming download->Hardware Test B: Schematic/HDL text input->Adaptation->Comprehensive->Functional simulation->Programming download->Hardware test C: Schematic/HDL text input->Functional simulation->Comprehensive ->Programming download->Adaptation->Hardware test D: Schematic/HDL text input->Adaptation->Functional simulation->Comprehensive->Programming download->Hardware test answer: [ Schematic/HDL text input->Functional simulation->Synthesis->Adaptation->Programming download->Hardware test] 6. Question: EDA in the field of modern electronic system design adopts a bottom-up design method . Options: A: Correct B: Wrong Answer: [Wrong] Analysis: [Top-down] 7. Question: The process of converting a hardware description language into a hardware circuit is called compilation. Options: A: Correct B: Wrong Answer: [Error] Analysis: [Comprehensive] 8. Question: IP core plays a very important role in EDA technology and development. IP provided in HDL is called hard IP. Options: A: Correct B: Wrong Answer: [Wrong] Analysis: [Soft] 9. Question: Functional simulation is a specification test for design input. Passing this kind of simulation can only mean that the compilation has passed, indicating that the design meets certain grammatical specifications. However, there is no guarantee that the design functionality will meet expectations. Options: A: Correct B: Wrong Answer: [Wrong] Analysis: [Behavioral Simulation] 10. Question: Functional simulation is a post-simulation performed after layout and wiring. The wiring delay is taken into account during the simulation, which is closer to the actual working condition of the chip. . Options: A: Correct B: Wrong Answer: [Wrong] Analysis: [Timing Simulation] Lecture 33 Digital System Design Example Lecture 33 Digital System Design Example - Unit Test 1. Question: In the variable section of AHDL, you can declare a A specific actual logical function that is independently applied is called a ( ) statement. Options: A: Process B: Instance C: Function D: Assignment Answer: [Example] 2. Question: AHDL nodes and three-state nodes are equivalent to design ( ) inside the circuit can complete the transmission of internal signals. Options: A: Register B: Flip-flop C: Latch D: Connecting line Answer: [Connecting line] 3. Question: In AHDL, use ( ) type nodes To declare signal line nodes including high, low level and high resistance states. Options: A: TRI_STATE_NODE B: NODE C: JKFFE D: SRFFE Answer: [TRI_STATE_NODE] 4. Question: The register declaration of AHDL includes the declaration of ( ). Options: A: Registers and flip-flops B: Flip-flops and latches C: Registers and latches D: Connection lines Answer: [Flip-flops and latches] 5. Question: AHDL line comments start with the symbol ( ) , comment to the end of this line. Options: A:/ B:// C:- D:/ Answer: [–] 6. Question: In the line comment symbols of AHDL, ( ) is used to represent the predefined logic level (Logic Level) Options: A: EXP B:DFF C:JKFF D:TRI Answer: [TRI] 8. Question: The user can use a ( ) statement to configure a changing name for a state machine. It can be defined in the current file or from another file. Introduction. Options: A: Alias of state machine B: Input C: Output D: Bidirectional B: Input C: Output D: Bidirectional Answer: [Alias of state machine B: Input C: Output D: Bidirectional ] 9. Question: MAX +plus II is ( ). Options: A: High-level language B: Hardware description language C: EDA tool software D: Comprehensive software Answer: [EDA tool software] 10. Question: Use quartus II tool software to realize schematic design input, should Use ( ) force formula. Options: A: Graphic editing B: Text editing C: Symbol editing D: Waveform editing Answer: [Graphic editing] 11. Question: The circuit schematic file input using the graphic editing mode of quartus II must pass ( ) to conduct simulation verification. Options: A: Edit B: Compile C: Comprehensive D: Programming Answer: [Compile] 12. Question: The main purpose of generating a component symbol for a graphics file in the quartus II integrated environment is ( ). Options : A: Simulation B: Compilation C: Synthesis D: Called by high-level circuit design Answer: [Called by high-level circuit design] [Assignment] Lecture 33 Digital System Design Examples Lecture 33 Digital System Design Examples - Unit Assignment 1. Question: Briefly describe the design process of schematic design method. Scoring rules: [The specific design process includes design input, functional simulation, synthesis, post-synthesis simulation, constraint setting, implementation, post-layout simulation, generating configuration files and configuring FPGA] 2. Question: Design a 4-bit FPGA with carry output BCD counter (requires an INCLK clock input, output 4-bit BCD code, carry output terminal CO) Scoring rules: [Sub-design end (25 points), 5 points will be deducted for missing one, 1 point will be deducted for wrong or missing statements, logic end (25 points) points), 1 point will be deducted for wrong or missing statements] [Assignment] Lecture 32 Preliminary HDL Design Lecture 32 Preliminary HDL Design - Unit Assignment 1. Question: Explain what are the characteristics of Verilog HDL, VHDL and AHDL languages? Grading rules: [ AHDL Verilog HDL VHDL ] [Assignment] Lecture 34 Application of EDA Technology in Digital Design Lecture 34 Application of EDA Technology in Digital Design - Unit Assignment 1. Question: Use Quartus II software to complete tasks with hours, minutes and seconds Build the digital clock circuit and download it to the FPGA development board of the experimental box, and use the equipment provided by the experimental box to test the digital clock function. The design idea of this experiment is a hierarchical structure, including four sub-modules: clock module, base conversion module, digital display decoder and digital tube display module. The FPGA crystal oscillator frequency used is 40MHz. First, use it to get a 1Hz clock and then get the clock module. Input the hours, minutes and seconds output by the clock module into the hexadecimal conversion module to get the decimal value and then input it into the LED display module. Scoring rules: [Clock module, base conversion module, digital display decoder and digital tube display module, 20 points for each module, 1 point will be deducted for incorrect writing or missing a sentence, and the last top-level design drawing will be 20 points. ] Lecture 34 Application of EDA Technology in Digital Design Lecture 34 Application of EDA Technology in Digital Design - Unit Test 1. Question: When using QuartusⅡ tool software to create simulation files, the ( ) method should be used. Options: A: Graphic editing B: Text editing C: Symbol editing D: Waveform editing Answer: [Waveform editing] 2. Question: When using the Quartus II tool software to modify design component symbols, the ( ) method should be used. Options: A: Graphic editing B: Text editing C: Symbol editing D:Waveform Editing Answer: [Symbol Editing] 3. Question: A design entity can have one or more ( ). Options: A: Entity B: Structure C: Input D: Output Answer: [Structure] 4. Question: The nodes and three-state nodes of AHDL are equivalent to () inside the designed circuit, which can complete the transmission of internal signals. Options: A: Register B: Flip-flop C: Latch D: Connection line Answer: [Connection line] 5. Question: In AHDL, use () type nodes to declare signal lines including high, low level and high resistance states. Node. Options: A: TRI_STATE_NODE B: NODE C: JKFFE D: SRFFE Answer: [TRI_STATE_NODE] 6. Question: The register declaration of AHDL includes the declaration of (). Options: A: Register and flip-flop B: Flip-flop and latch C: Registers and latches D: Connecting wires Answer: [Flip-flops and latches] 7. Question: For the signal assignment statement in the process, the signal update is ( ) Options: A: Completed in sequence B: Ratio variable Complete faster C: Complete at the end of the process D: None of them are correct Answer: [Complete at the end of the process] 8. Question: After the design input is completed, the design file should be processed ( ) immediately. Options: A: Edit B: Compile C: Functional simulation D: Timing simulation Answer: [Functional simulation] 9. Question: Execute the ( ) command of Quartus II to check the design circuit errors. Options: A:Create Default Symbol B:Compiler—Compilation C:Simulator—Timing simulation D:Timing Analyzer—Timing analysis Answer: [Compiler—Compilation] 10. Question: Users can use a ( ) statement to give A state machine configures a changing name, which can be defined in the current file or imported from another file. Options: A: Alias of state machine B: Input C: Output D: Bidirectional Answer: [Alias of state machine] Lecture 6 Karnaugh Map Simplification of Logical Functions Lecture 6 Karnaugh Map Simplification of Logical Functions – Unit Test 1. Question: The logical adjacent term that is not the minimum term ABCD is ( ) Option: A:

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Answer: 【

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】 2. Question: The standard AND or expression is composed of ( ). Options: A: The minimum term is the same or B: The maximum term is the same as C: The AND term is the same or D: The OR term is the answer: [The minimum term is the OR] 3. Question: In the Karnaugh map of the 4-variable logistic function, there are ( ) squares and

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Adjacent options: A:1 B:2 C:3 D:4 Answer: [4] 4. Question: If the logical function F(A,B,C)=∑m(2,3,5,7),G (A,B,C)=∑m(0,2,5,6), then the result of the AND of F and G is ( ) Options: A:AB B:1 C:

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D:0 Answer: [

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] 5. Question: When

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When , two minterms of the same logical function

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( ). Options: A:

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C:1 D:0 Answer: [0] 6. Question: In the Karnaugh map shown, the simplified logical function is ( )

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Options: A:AB+BC+AC B:

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Answer: 【

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】 7. Question: Use Karnaugh map to simplify the logical function. The final expression of the simplification is unique. Options: A: Correct B: Wrong Answer: [Wrong] 8. Question: The minimum term of n variables should contain the product term of all n variables. In the product term, each variable can only appear once in the form of the original variable. Options: A: Correct B: Wrong Answer: [Wrong] 9. Question: The criterion for formulating the simplest AND or formula is: in the AND or formula, the number of AND terms is the minimum, and the number of variables in each AND term is the minimum. Options: A :Correct B:Wrong answer: [Correct] 10. Question: If two functions have different truth tables, then the two logical functions must not be equal. Options: A: Correct B: Wrong Answer: [Correct] Lecture 14 Adder Adder - Unit Test 1. Question: The input (A, B, C) output waveform (X, Y) of a combinational logic circuit is as shown in the figure below is shown, then its logical function is ( )

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Answer: [Remaining 3 codes] [Homework] Lecture 12 Decoder Decoder Unit Homework 1. Question: The combinational logic circuit composed of the 3-line to 8-line decoder 74LS138 and the gate circuit is as shown in the figure below. Among them, the input signal

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is the address line. Try writing the address realized by each output of the decoder.

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Judging rules: 【

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10 points for each correct output address, and the rest

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5 points for correct output address.

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] [Assignment] Lecture 14 Adder Adder - Unit Assignment 1. Question: Please use 742LS83 to design and implement a controllable remainder 3 code to 8421BCD code and 8421BCD code to remainder 3 code conversion circuit. When X=0, the 8421BCD code to the remainder 3 code is realized, and when X=1, the remainder 3 code is realized to 8421BCD code. Scoring rules: [ +1), complement operation.

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Scoring rules: [The expression of B number is

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, worth 10 points, 5 points will be deducted for each wrong one; MN=00,

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, the output result is equivalent to S=I+0;MN=01,

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, the output result is equivalent to S=I+2; MN=10,

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, the output result is equivalent to S=I+3;MN=11,

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, the output result is equivalent to S=I+5. When MN=00~11, each B number value is 5 points, and the expression of S is 5 points, a total of 40 points]

Digital logic and digital system design (Yuan Xiaoping) MOOC reference answers

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