mathematical logic:
The first part of logical algebra
Handwritten a key mind map by yourself, the words are ugly, so let’s take a look
One. Base conversion
The original code's complement code 8421BCD code gray code
can be practiced through the exercises in the first chapter on page P15 of the book
two. Gates (Book P19 Logic Gates: Symbols in common use in the world used to symbolize national standard symbols)
- AND operation
- OR operation
- Non-operation
- And and not logic (first AND, then negation)
- Or-not logical (first OR, then negate)
- And or not logical (first AND, then OR, then negation)
- XOR logic
(1) XOR of odd number of variables = XOR of same or even number of variables = same or not - XOR logic
three. Basic operation law
four. Inverse function inversion rule dual function dual rule
- Inversion rules (inversion function)
·change + + change· 0 change 1 1 change 0 The original variable becomes the inverse variable The inverse variable becomes the original variable - Duality rule (seeking dual function) is used to prove whether a function is equal or not
· change + + change · 0 change 1 1 change 0 · change + + change · The same applies to XOR and XOR
Fives. Minimum item maximum item
-
The sum of minimum terms
Standard AND expression: each AND term contains all input variables
(the original variable is recorded as 1, and the inverse variable is recorded as 0), which
means: the number of minimum terms of n variables: 0~ 2^n- 1
Nature:
-
The product of the largest terms
Standard OR and expression: each OR term contains all input variables
(the original variable is recorded as 0, the inverse variable is recorded as 1, and the opposite of the smallest term)
means: n The number of the largest term of the variable: 0 ~ 2^n-1
Nature:
six. Logical function expression
- Expand the function into the form of "sum of products", "simplest AND OR expression"
- Expand the function into the form of "product of sum", "simplest OR and expression"
Method: - Formula method
- Karnaugh map (sequence: 00 01 11 10)
Note: When simplifying by Karnaugh map:
1) First circle "1" in only one case, and the area to be circled is the largest (1,2,4,8,16) ) [No 6]
2) Draw a circle and draw a line and write the AND (or)
3) After drawing , check whether there is a circle and all the elements in it have been circled by other circles, if it is , You have to remove it (this step will not occur strictly in accordance with the first step)
4) The simplest OR expression cannot be converted into the simplest OR expression
5) There are many "1" positions in the Karnaugh map and it is very complicated When circled "0", you can consider circle "0", but it should be noted that when circle "0", negative logic is used.
6) In the Karnaugh diagram, mark "×" or "d" in the position of irrelevant items, when circled , Draw a circle from the angle of "1" or "0", and take irrelevant items into consideration.
7) If it is simplified by the truth table, fill in the card corresponding to the rows of the truth table output as 1 Simplification
The second part is the analysis and design of combinational logic circuit
A brief overview
The basic characteristics of a combinational logic circuit: ①No feedback in structure, ②No memory in function, ③The output of the circuit at any moment is completely determined by the input signal at that moment, and has nothing to do with the past input and past state.
1. Analysis of combinational logic circuit
Example: Analyze the function of the circuit in the following diagram.
Steps of analysis:
(1) Write down the logic expression level by level from the logic circuit diagram.
(2) Reduce the logical expression to the simplest AND OR expression
(3) Draw the truth table
(4) The function of the analysis circuit. It is
known that A and B are input variables, and S and C are output variables. From the first three lines of the truth table, S is
the addition of A and B. C is always 0. In the case of four lines, the input of A and B are both 1. If according to the previous guess
, S is adding A and B. At this time, S should be 10 in binary, but the value of S is 0. At this time, C
Is 1, it is not difficult to think that C is used to represent the carry bit, so the function of this circuit is a binary adder
, A is the addend, B is the addend, S is the sum of the two, and C is the carry bit , But because the adder does not
consider the carry from low to high, the adder is a half adder.
Follow the above steps:
(1) Write the logic expression level by level from the logic circuit diagram
(2) Simplify the logical expression into the simplest AND OR expression
(3) Draw the truth table
(4) Analyze the function of the circuit.
Observing the truth table, we can see that when M=1, Y=A; when M=0, Y=B; therefore, the circuit is an alternative
circuit.
2. Design of combinational logic circuit
Examples: 1. Design a full adder.
Steps:
(1) Analyze the causality of the event and determine the input variable and output variable. The
full adder has three input variables, defined as A, B, Cin, and two output variables, define S and Cout.
(2) Define the meaning of the logic state and assign values to the variables.
When A=1, it means that the value of A is input at this time. When A=0, it means that the value of A is input at this time is 0.
B, Cin Similarly;
when Cout=1, it means that the sum of A, B, and Cin generates a carry bit; when Cout=0, it means that the sum of A, B, and Cin does
not generate a carry;
when S=1, it means A, B , Any one of the variables in Cin takes the value 1, and the other two variables take the value 0,;
or A, B, Cin are all 1, when S=0, it means any two of the variables in A, B, Cin The value is 1, and the
other variable is 0.
(3) List the truth table according to the given causality
(4) Write the corresponding logic function expression from the truth table
(5) Draw the logic circuit diagram from the logic function expression
3. Encoder and decoder
1. Encoder: Convert decimal to binary
. Effectiveness of input value: ①Original variable input=positive logic input=high power frequency input=some input pin=1
②inverse variable input=negative logic input=low power frequency input=
Some priority encoders are also introduced for a certain input pin=0 , please refer to P86 for details.
2. The decoder (it is the reverse process of the encoder, which converts the binary system to the decimal system)
uses the 38 decoder as the pump: the 38 decoder has three enable terminals 1 S, 2 S, 3 S (one high and two low ), three address
selection terminals A0, A1, A2 (respectively connected to three external input variables), eight output terminals
Zi (i=0,1,2·····7), of which, each Zi mi (mi is composed of three variables A0A1A2). For
example, when Z0 =0 is valid, Z0 A0 A1 A2, A0A1A2 =000.
How to design a full adder with 38 decoder?
Fourth, the data selector
Function: Select one data from multiple inputs as output.
Common data selectors have 2 to choose 1, 4 to choose 1, 8 to choose 1, 16 to choose 1, take 4 to choose 1 as an example, A1A0 is the address
selection terminal, D0D1D2D3 is the input terminal, and Z is the output terminal. The choice here means A1A0 is used to select
D0D1D2D3 as the output.
Key point: How to use the data selector to design a circuit with perfect functions?
Give a chestnut: How to design a full adder with 8 out of 1 data selector?
Analysis: The full adder has three input variables and two output variables; the three input variables ABCin can be connected
to the three data input terminals A0A1A2 of the 8 out of 1 data selector, so it is easy to solve the input variables;
But. . . How to represent the output variables S and Cout of the full adder? Because the 8-to-1 data selector has only
one output terminal, at this time, one 8-to-1 is not enough, and two 8-to-1 data selectors
are needed .
Full adder: S=m1+ m2+ m4+ m7
Cout = m3 + m5 + m6 + m7
Steps:
(1) Consider making the three address input terminals of the data selector correspond to the three input variables of the full adder
(2) Use The expansion formula corresponds to the two formulas of the full adder. The two 8-to-1 A2A1A0 must correspond to ABC.
3) The two 8-to-1 outputs are S and C out respectively.
How to design a full adder with a 4-to-1 data selector?
Analysis: 4 out of 1 data selector is similar to 8 out of 1 data selector, both data selectors are used,
However, it is more difficult. The difficulty is that the data selector of 4 out of 1 has only two address input terminals, while the full
adder has three input variables. Then, how to use the data selector of 4 out of 1 to indicate the third Input variables?
Full adder: S=m1+ m2+ m4+ m7
Cout = m3 + m5 + m6 + m7
When calculating S, substituting AB=00, 01, 10, 11 into the above equations, and the following table can be obtained.
When calculating Cout, substituting AB=00, 01, 10, and 11 into the above formulas, the following table can be obtained.
It can be seen from the above that Cin is connected to D1 and D2, D0 is grounded, and D3 is connected to Vcc or +5V.
From this, the available circuit diagram is:
The third part of sequential circuit analysis and design
Chapter 5: Triggers
Preface: The
flip-flop itself is composed of multiple logic gates. Different from the combinational logic circuit, the flip-flop has the output
feedback to the input signal, so the flip-flop has the function of memorizing the input information.
5.1.1 Circuit structure and characteristics of flip-flops Some supplements
on page 115 of the book
:
- The flip-flop is a bistable circuit.
Bistable circuit:
In electronic circuits, the characteristic of the bistable circuit is that the circuit is always in its original
stable state without external trigger signals . Under the action of an external input trigger signal, the bistable circuit flips from one stable state to another stable
state. Because it has two stable states, it is called a bistable circuit.
My understanding:
It has two stable states: 0 state (Q=0, Q non=1) and 1 state (Q=1, Q non=0).
Under different input conditions, it can be set to 0 State or 1 state
When the input signal disappears, the set state can be maintained - The function of the timing (clock) end CP
of the flip-flop is to trigger our flip-flop. Why do some triggers need a CP side?
Explanation: There is no trigger on the CP terminal
on page 119 of the book. The
input signal is directly added to the input terminal of the output gate.
There is a small circle on the CP terminal, which means that when the CP terminal is a falling edge, the trigger will work and the input signal will be blocked. receiving
CP side not spicy small circles, to the rising edge of the trigger CP represents only the working end, the input signal is accepted
when clocked RS flip-flop must CP = 1, the flip-flop before working. (Page 120 on the book)
5.1.2 The logic function and classification of flip-flops
According to the circuit structure classification:
basic RS flip-flop, clock-controlled RS flip-flop, synchronous flip-flop, master-slave flip-flop, edge flip-flop
Classification according to the circuit logic function:
RS flip-flop, D trigger is, JK flip-flop, T flip-flop, T 'flip-flop
to define the basic trigger and clocked flip-flops:
a little above the book 116
5.2 basic RS flip-flop
circuit diagram: 116 book
inputs: R non, S non
output: Q , Q non-
characteristic equations and constraints are very important!
Why is there such a constraint?
Below page 116 of the book (4)
RS flip-flop summary:
3. No matter what kind of RS, the characteristic equation is the same
. 4. The constraints of the NAND gate and the NOR gate are mathematically equivalent, but they are not equal in the circuit price
constraints clocked RS in RS added a substantially CP = 1 constraint is
the primary constraint RS from the CP added a constraint on the falling edge of RS substantially
on end 5. R diet is called a reset terminal, reset. When this terminal is valid, state 1 will be set to state 0
6. S terminal is customarily called the reset terminal, Set. When this terminal is valid, state 0 will be set to state 1
5.3 D flip-flop,
focus on mastering the characteristic equation
5.4JK flip-flop
Focus on mastering the characteristic equation.
Note: When J=1 and K=1, Q(n+1)=Qn is not, which becomes a T'flip-flop.
5.5 Other flip-flops
T flip-flops, T'flip- flops, it’s almost enough to write down the characteristic equations.
5.7 Interconversion of flip-flops
. Important page 129 in the book.
5.8 Application of flip-flops.
Frequency divider: 132 pages in the
book. Frequency division, if you want frequency division by 4, you need 2 flip-flops, and so on.
There are also edge D flip-flops used in the book, but we can also use JK flip-flops to achieve, as long as J=1, K=1.
Chapter Six
6.1 Analysis steps of sequential circuit
.
7. Circuit diagram on page 141 of the book. Observe whether it is a synchronous sequential circuit or an asynchronous sequential circuit. Observe the flip-flop type, JK or D, etc.
8. Write the clock equation, drive equation (excitation equation), output equation and state equation
9. List the truth table
10. Draw the state transition Figure
11. Determine the logic function of the circuit
Effective cycle, some self-starting concept book on the middle of 143
Points to note:
12. The clock equation of the synchronous sequential circuit is like CP=CP0=CP1=CP2. 2. When listing the truth table, CP should be listed.
13. The logic function may not be visible at a glance. You can try to exchange it. The order of Q1, Q2, Q3.
6.2 Sequential circuit design steps
1. Establish the original state diagram
2. State simplification
3. State allocation and state coding
4. Select the trigger type
5. List the truth table
6. Discuss the self-starting problem
7. Draw the circuit diagram