Level 1: Design of a full adder - gate-level primitive structure
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The final answer for this level:
mission details
This task: describe the full adder using the gate-level primitive structure.
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full adder
The full adder FA (Full Adder) is to realize the addition of two 1-bit binary numbers (x, y) and from the low-order carry (Ci or Cin) to generate a combination of sum (s) and carry output (Ci+1 or Cout) logic circuit. The schematic diagram of the circuit is as follows:
Structural Definition of Logic Circuits
Verilog contains a series of gate-level primitive structures corresponding to general-purpose logic gate circuits. A logic gate can be represented by defining its function name, input and output. Gate-level primitive structures can be used to define larger-scale circuits. The gate-level primitive structure is also called gate instantiation. The syntax is as follows:
gate_name [inst_name](output_port,input_port{,input_port});
For example, a 2-input AND gate whose output is y and whose inputs are x1 and x2 can be represented as:
and( y, x1, x2 );
A 3-input OR gate can be defined as:
or( y, x1, x2, x3 );
A 3-input XOR gate can be defined as:
xor( y, x1, x2, x3 );
programming requirements
According to the above circuit diagram, supplement the code in the editor on the right, and note that the interface signal is based on the name in the code on the right.
test introduction
The platform tests the code you write.
Level 2: Design of a Full Adder—Continuous Assignment
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The final answer for this level:
mission details
The task of this level: use continuous assignment to describe the full adder.
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full adder
The full adder FA (Full Adder) is to realize the addition of two 1-bit binary numbers (x, y) and from the low-order carry (Ci or Cin) to generate a combination of sum (s) and carry output (Ci+1 or Cout) logic circuit. The schematic diagram of the circuit is as follows:
The logical expression of the full adder is as follows:s=x⊕y⊕Cin Cout=xy+xCin+yCin
continuous assignment assign
In Verilog, and, or, and not operations are represented by &, |, ~ respectively, and the keyword assign is used to continuously assign the output signal. The syntax is as follows:
assign net_assignment{,net_assignment};
programming requirements
According to the above circuit diagram, supplement the code in the editor on the right, and note that the interface signal is based on the name in the code on the right.
test introduction
The platform tests the code you write.
Level 3: Design of a Full Adder - Behavior Description (Arithmetic Operations)
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The final answer for this level:
mission details
This level task: Describe a full adder using the behavior of arithmetic operations.
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The full adder FA (Full Adder) is to realize the addition of two 1-bit binary numbers (x, y) and from the low-order carry (Ci or Cin) to generate a combination of sum (s) and carry output (Ci+1 or Cout) logic circuit. Using arithmetic operations, adding circuits can be described more abstractly and succinctly.
arithmetic operations
The operator of arithmetic operation addition in Verilog is +, for example, the summation of half addition operation can be expressed as follows:
sum = a + b;
Bit concatenation operator {s1,s2}
Concatenate the two signals a and b into a vector (multi-bit binary signal), as follows:
{a,b}
Concatenate the carry output Cout of the full adder with the sum s as follows:
{Cout,s}
programming requirements
Supplement the code in the editor on the right, paying attention to the use of bit concatenation and arithmetic operations.
test introduction
The platform tests the code you write.
Level 4: 4-Bit Adder Design - Module Instantiation
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The final answer for this level:
mission details
This level task: instantiate 4 full adders (which can be named stage0, stage1, stage2, stage3 or U0, U1, U2, U3, etc.) with the full adder module designed in the previous level to build a 4-bit traveling wave carry addition device.
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include keyword
Introduce other circuit modules into the current module and instantiate them. The syntax is as follows:
`include "[path/]<module_name.v>"...module_name [instanse_name](portmap)//括号中为端口映射
For example, the circuit module in the first level is introduced and instantiated:
`include "fulladd_gates.v" //引入第一关中的电路模块...fulladd_gates U0 (...);//实例化一个名为U0的模块，括号中按顺序给定对应信号fulladd_gates U1 (...);//实例化一个名为U1的模块...
vector (vector)
The vector in Verilog is similar to the array in C language, but the definition form is different, as follows:
input [3:0] X; //input为输入信号wire [3:1] C; //wire为电路内部连线
programming requirements
According to the prompt, add the code in the editor on the right.
Common mistakes
When a circuit file (module) is imported, there should be no spaces before and after quotation marks, such as
test introduction
The platform tests the code you write.
Level 5: n-bit adder design - arithmetic operation
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The final answer for this level:
mission details
This task: Build an n-bit adder with arithmetic operations and perform overflow detection.
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parameter setting parameter
Verilog uses the parameter keyword to define parameters, such as defining the adder bit width:
parameter n = 16;
The parameters can be reassigned when the module is instantiated, as follows:
addern_arith U1(...);defparam U1.n = 8 ;
overflow detection
One of the overflow detection principles of the addition operation of signed numbers (X+Y=S): X and Y have the same sign and the sign of the result S is opposite to that of the result S. The logical expression is as follows:
overflow = Xn − 1 In − 1 Sn − 1 + Xn − 1 In − 1 Sn − 1
The second overflow detection principle of the addition operation of signed numbers (X+Y=S): If the carry of the sign bit is opposite to the carry of the most significant bit, it overflows. The logical expression is as follows:
overflow=Cn⊕Cn−1
The third overflow detection principle of the addition operation of signed numbers (X+Y=S): Use double sign bits, and the two sign bits of S are opposite to overflow, and the logical expression is as follows:
overflow=Sn+1⊕Sn
programming requirements
According to the prompt, add the code in the editor on the right.
test introduction
The platform tests the code you write.
Level 6: 8421BCD code adder design (1-digit decimal)
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The final answer for this level:
mission details
The task of this level: Design the 8421BCD code adder (1-digit decimal).
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Correction is made on the basis of 4-bit binary addition (X+Y=Z) to obtain the result S of 1-digit decimal addition. If Z<=9, add 0 for correction, that is, S=Z; if Z>9, add 6 for correction, that is, S=Z+9.
programming requirements
According to the prompt, add the code in the editor on the right.
test introduction
The platform tests the code you write.