Hour, minute and second electronic clock design report
aim of design
(1) Master the design method of the hour, minute and second electronic clock
(2) Understand the composition and working principle of the hour, minute and second electronic clock
(3) Through the design and implementation of comprehensive experimental projects, further deepen the theoretical teaching and practical training of experimental software and hardware platforms , Make full preparations for design experiments.
Design goals
(1) Accurate timing, displaying hours, minutes, and seconds in digital form.
(2) The hourly timing is in the form of "23 turns 0".
(3) Add the function of displaying the week.
(4) Add the alarm clock function, the alarm time is set by the user.
According to the module, explain the VerilogHDL program code (with comments)
module clock(h_alarm1,h_alarm2,m_alarm1,m_alarm2,s_alarm1,s_alarm2,data,hour1,hour2,minute1,minute2,sec1,sec2,reset,sign1,sign2,sign3,sign4,sign5,sign6,clk,alarm,adapt1,adapt2,adapt3,adapt4,adapt5,adapt6);
input reset,clk,adapt1,adapt2,adapt3,adapt4,adapt5,adapt6;
//输入reset清零端，clk脉冲
//adapt1~6设置闹钟时分秒的高低位
output [4:1]sec2,minute2,hour2,h_alarm2,s_alarm2,m_alarm2;
output [3:1]sec1,minute1,hour1,data,h_alarm1,s_alarm1,m_alarm1;
//输出时分秒的高低位，星期
//输出设置的闹钟时间
output sign1,sign2,sign3,sign4,sign5,sign6,alarm;
//sign1~6进位判断,alarm闹钟信号显示
reg [4:1]sec2,minute2,hour2,h_alarm2,s_alarm2,m_alarm2;
reg [3:1]sec1,minute1,hour1,data,h_alarm1,s_alarm1,m_alarm1;
wire sign1,sign2,sign3,sign4,alarm,sign5,sign6;
assign sign5=(sec2==4'b1001)?1:0;
//秒的低位满9向上进位信号
assign sign6=((sec1==3'b101)&&sign5)?1:0;
//下级传来进位信号后，秒的高位向上进位的信号
assign sign1=((minute2==4'b1001)&&sign6)?1:0;
//分的低位向上进位信号
assign sign2=((minute1==3'b101)&&sign1)?1:0;
//分的高位向上进位信号
assign sign3=(((hour2==4'b1001)||((hour1==3'b010)&&(hour2==4'b0011)))&&sign2)?1:0;
//时的低位向上进位信号（此时有两种情况①hour2满9进位，②23小时的情况下进位）
assign sign4=((hour1==3'b010)&&sign3)?1:0;
//时的高位向上进位信号
assign alarm=((hour1==h_alarm1)&&(hour2==h_alarm2)&&(minute1==m_alarm1)&&(minute2==m_alarm2)&&(sec1==s_alarm1)&&(sec2==s_alarm2))?1:0;
//判断是否为闹钟时间？若是，则发送闹钟信号alarm=1
//对sec2（秒低位）进行的操作
always @(posedge clk)
begin
if(reset)//高有效，清零
sec2<=4'b0000;
else if(sec2==4'b1001)//如果满9，sec2清零
sec2<=4'b0000;
else sec2<=sec2+1;//否则+1
end
//对sec1（秒高位）进行的操作
always @(posedge clk)
begin
if(reset)
sec1<=3'b000;
else if(sign5)//秒低位传来进位信号
if(sec1==3'b101)//若此时秒高位=5，则清零，反之则+1
sec1<=3'b000;
else sec1<=sec1+1;
end
//对min2（分低位）进行的操作
always @ (posedge clk)
begin
if(reset)
minute2<=4'b0000;
else if(sign6)//秒高位传来进位信号
if(minute2==4'b1001)//若此时分低位=9，则清零，反之则+1
minute2<=4'b0000;
else
minute2<=minute2+1;
end
//对min1（分高位）进行的操作
always @ (posedge clk)
begin
if(reset)
minute1<=3'b000;
else if(sign1)//分低位传来进位信号
if(minute1==3'b101)//若此时分高位=5，则清零，反之则+1
minute1<=3'b000;
else
minute1<=minute1+1;
end
//对hour2（时低位）进行的操作
always @ (posedge clk)
begin
if(reset)
hour2<=4'b0000;
else if(sign2) //分高位传来进位信号
case(hour1)//按照hour1（时高位）来分情况讨论
3'b000://时高位为0时
begin
if(hour2==4'b1001)//若时低位满9，则清零，反之+1
hour2<=4'b0000;
else
hour2<=hour2+1;
end
3'b001://时高位为1时
begin
if(hour2==4'b1001)//若时低位满9，则清零，反之+1
hour2<=4'b0000;
else
hour2<=hour2+1;
end
3'b010://时高位为2时
begin
if(hour2==4'b0011)//若时低位满3，则清零，反之+1
hour2<=4'b0000;
else
hour2<=hour2+1;
end
endcase
end
//对hour1（时高位）进行的操作
always @ (posedge clk)
begin
if(reset)
hour1<=3'b000;
else if(sign3)//时低位传来进位信号
if(hour1==3'b010)//若时高位满2，则清零，反之+1
hour1<=3'b000;
else
hour1<=hour1+1;
end
//对data（星期）进行的操作
always @ (posedge clk)
begin
if(reset)//清零时，data初始化为星期一
data<=3'b001;
else if(sign4)//时高位传来进位信号
if(data==3'b111)//若此时data为星期日，则置为星期一，反之+1
data<=3'b001;
else
data<=data+1;
end
//根据传来的adapt1信号，设置h_alarm1(闹钟时高位)的数值
always @ (posedge clk)
begin
if(adapt1&&(h_alarm1==3'b010))
//传来adapt1信号，当此时闹钟时高位为2时，将闹钟的时高位数值置为0，反之继续+1
h_alarm1<=3'b000;
else if(adapt1)
h_alarm1<=h_alarm1+1;
end
//根据传来的adapt2信号，设置h_alarm2(闹钟时低位)的数值
always @ (posedge clk)
begin
if(adapt2&&(h_alarm2==4'b1001))
//传来adapt2信号，当此时闹钟时低位为9时，将闹钟的时低位数值置为0，反之继续+1
h_alarm2<=4'b0000;
else if(adapt2)
h_alarm2<=h_alarm2+1;
end
//根据传来的adapt3信号，设置m_alarm1(闹钟分高位)的数值
always @ (posedge clk)
begin
if(adapt3&&(m_alarm1==3'b101))
//传来adapt3信号，当此时闹钟分高位为5时，将闹钟的分高位数值置为0，反之继续+1
m_alarm1<=3'b000;
else if(adapt3)
m_alarm1<=m_alarm1+1;
end
//根据传来的adapt4信号，设置m_alarm2(闹钟分低位)的数值
always @ (posedge clk)
begin
if(adapt4&&(m_alarm2==4'b1001))
//传来adapt4信号，当此时闹钟分低位为9时，将闹钟的分低位数值置为0，反之继续+1
m_alarm2<=4'b0000;
else if(adapt4)
m_alarm2<=m_alarm2+1;
end
//根据传来的adapt5信号，设置s_alarm1(闹钟秒高位)的数值
always @(posedge clk)
begin
if(adapt5&&(s_alarm1==3'b101))
//传来adapt5信号，当此时闹钟秒高位为5时，将闹钟的秒高位数值置为0，反之继续+1
s_alarm1<=3'b000;
else if(adapt5)
s_alarm1<=s_alarm1+1;
end
//根据传来的adapt6信号，设置s_alarm2(闹钟秒低位)的数值
always @(posedge clk)
begin
if(adapt6&&(s_alarm2==4'b1001))
//传来adapt6信号，当此时闹钟秒低位为9时，将闹钟的秒低位数值置为0，反之继续+1
s_alarm2<=4'b0000;
else if(adapt6)
s_alarm2<=s_alarm2+1;
end
endmodule
Timing simulation diagram
Figure
It can be seen from Figure 1 that sec2->sec1->minute2 is successfully rounded and the week data=1. Two pulses of adapt6 (lower alarm seconds) and one pulse of adapt5 (high alarm seconds) are set during input, that is, the alarm is set to the 12th second. The alarm in Figure 1 shows the waveform change at the 12th second.
It can be seen from Figure 2 that minute2->minute1->hour2 is successfully rounded.
It can be seen from Figure 3 that hour2->hour1->data is carried successfully.
It can be seen from Figure 4 that the week function is implemented, and data is reset to 1 on the eighth day after every day data+1.
Experiment summary
In this experiment, I completed the three functions of basic timing, displaying the day of the week, and setting an alarm. Functional realization is normal and feasible, but I think there is still room for improvement. Multiple variables are defined when setting the alarm time. Although it can be clear when adjusting the alarm clock, it will be a waste of cost in terms of the actual application of the clock, and the disadvantages outweigh the advantages.
This special experiment used the usual theoretical knowledge, not only deepened my understanding of the working principle of clock, but also stimulated my creativity, and made me realize that designing devices must be considered from many aspects, especially Consider the practicality of the clock.