A digital circuit which often use some logic gates, such as "AND gate", "OR", "NAND" gate circuit and the like; an analog circuit which will often TTL level to CMOS level. Whether it is design or gate level conversion circuit, almost inseparable from the transistor. Analysis of the analog circuit will be in the "negative logic" circuit is a digital circuit inside the "NAND", scratch design process, look at the contents of which contains a simple circuit together.
This circuit should be very familiar with the above, it is often used in level conversion circuit. As shown in the figure, the control signal is 3.3V, but in the collector of the transistor, i.e. Vce can reach 5V, level conversion can be achieved.
Further, it can be seen from the waveform phase of the pulse signal and the output voltage Vce of the control circuit: when the control signal is high, the output signal is 0V; when the control signal is low, the output signal is 5V. If we control both the level and the upper end VCC_5V R1 unified signal, the circuit implementation of the negative logic function.
After the above analysis, the circuit at the theoretical level, no problem to achieve the function, it is not the design of the circuit is reasonable it? Can be accurate to say that, no.
01. One unreasonable: base of the transistor-level resistance value
Belonging to the flow control transistor type three-terminal device stream, when Vbe≥0.7V, i.e., a current Ib flows, Ic current flows there. And whether it is logically inverted circuit, or a level shifter circuit, the transistor is used as a "switch", i.e., triode "saturation" and "off" state two.
For the circuit to work properly, must Ib≥1mA, the transistor is fully turned on to work in the state of saturated conduction. Since the control signal is 5V, the R2 value is to meet the conditions 5k. Taking into account the resistor values, fetch 4.7k here. R1 is a pull-up resistor, 1k taken here. Why take the R2 1k wrong with that? Here is the departure from power level. The control signal is 5V, Vbe = 0.7V, then the power generated by the resistor R2 P = U² / R, when R2 is increased, the power consumption is reduced.
02. unreasonable two: the transistor base configuration appears high
A circuit in which any one semiconductor device to allow only two states, either then high, then either a low level (see also some manual on-chip, floating unused pins, not discussed here ), is to avoid the emergence of a high-impedance state occurs. High impedance means is a base of the transistor unstable state.
当S1开关导通时，三极管的基极此时为高电平；当S1开关断开时，三极管的基极此时接R2，但是R2的左端悬空，即三极管的基极为高阻态（电平不确定）。既然电平不确定，就存在下面三个问题：
- 静电
- 雷击
- 电磁干扰
静电大家比较熟悉，冬天穿好衣服如果立马去开自己的笔记本电脑，经常会出现触电的感觉，这就是静电。而接触放电在瞬时可以达到4kV，如果刚好这个静电接触到R2的左端，那么三极管在这一瞬间就会误导通，甚至是损坏。所以经常会在产品上看到ESD防护等级要求，就是为了保证产品能过静电干扰。
雷击和静电破坏原理差不多，如果产品用在室外，碰上雷雨电气，R2左端会存在被几十KV雷击的危险，也会造成三极管的误导通，而且肯定被烧毁。
电磁干扰是因为在空气中存在着大量的电磁波，如果刚好在某个时候，周围存在一个非常大的电磁波被电路吸收，那么三极管还是存在误导通的风险。
因此，为了避免上面三种情况的发生，就要避免三极管的基极出现高阻态的情况。于是就在三极管的基极增加下拉电阻R3，保证开关断开时，基极接地。但是问题来了，R3的取值为多大呢？
R3的取值，从两个方面考虑，
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流过三极管基极的电流Ib≥1mA
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Vbe≥0.7V
由于R2的取值能够保证Ib，那是不是R3取2K，4.7K，5.6K 等，只要满足Vbe≥0.7V就可以呢？
03.不合理之三：没考虑三极管实际特性
半导体器件和导体不一样，像电阻是导体，流过电阻两端的电压和电流是同相位，但是半导体器件由于生产工艺的原因，无法避免的在一些器件上产生了寄生电容也叫杂散电容。三极管的开通和关断就不能按照电阻那样分析，开关闭合，三极管立马开通；开关关断，三极管立马关断，这是理想的状态。对于实际的电路，三极管的开通也是需要时间的。三极管的等效电路如图所示（不考虑Cbc和Cce对电路的影响）。
三极管要开通，基极将经历下面的过程:
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Ib电流对电容Cbe充电
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Cbe达到0.7V以后，三极管导通
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Cbe对be等效的PN结放电
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When the transistor is fully turned on, then Vce is 0, the transistor in the saturation region; when the transistor is fully closed, then Vce of 5V, the transistor is turned off in the work area. Vce from 0 to 5V during the process is the transistor turned off, this process has an enlarged intermediate state, and Boost state is that we do not wish it to appear in the design, thus turning off the transistor to be as quickly as possible. Obviously Cbe of the entire circuit, whether in the open or in the shutdown, have played a role in obstructing.
In order to accelerate the opening of the transistor to be slightly reduced R2, the charging current can be increased; in order to speed up transistor is turned off, R3 is clearly not the better the value.
According to experience, the transistor base resistance R2 taken 3.3K, R3 taken 2K, is more appropriate.
As can be seen from the above analysis, a simple circuit to be designed, content included is really too much, only to realize the function of theoretical analysis, the real product used in the circuit, is the need to go through many considerations, including packaging, model, price, power, manufacturability and so on.
Final design logic inversion circuit as shown in FIG.
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