Xilinx FPGA development of practical tutorial

Foreword

Finishing brief part of the book chapters, details can refer to read the original "Xilinx FPGA development of practical tutorial - Tian Yun of"!

 

1, Xilinx primitive Profile

Xilinx primitives provided by the FPGA development covers common areas, but only the corresponding configuration of the hardware to perform the corresponding primitive, not all of the primitives can be run on any of a chip.

This section describes the various types of Virtex-4 platform primitives.

Primitive functional classification, can be divided into:

• Computing components primitive;
• I / O port assembly primitive;
• Primitive register and latch;
• Clock components primitive;
• Processor component primitives;
• The shift register primitive;
• Check the configuration and assembly of primitives;
• RAM / ROM primitive assembly;
• Slice / CLB components primitive;
• Primitive gigabit transceiver assembly;

1.1 clock component primitives

Clock components include various global clock buffer, the global clock multiplexer, normal I / O local clock buffer, and advanced digital clock management module.

Primitive name	description
BUFG	Global Clock Buffers
BUFGCE	Global clock multiplexer, with the clock enable signal and the output state 0
BUFGCE_1	Global clock multiplexing buffer, with the clock enable signal and the output 1 state
BUFGCTRL	Global clock multiplexing buffer
BUFGMUX	Global clock multiplexing buffer, with the clock enable signal and outputs the state 0
BUFMUX_1	Global clock multiplexer, with the output state 0
BUFGMUX_VIRTEX4	During the Virtex-4 unique global clock multiplexing buffer
BUFIO	I / O port of the local clock buffer
BUFR	I / O port and a local clock buffer CLB
DCM_ADV	Digital clock management module with advanced features
DCM_BASE	Digital clock management module with basic characteristics
DCM_PS	Digital clock management module with the basic characteristics and the phase-shifting features
PMCD	Matching the phase of clock divider

Several components common clock briefly.

1.1.1 BUFG

BUFG global clock buffer having a high fan-out, usually automatically inferred from the synthesizer and used. Global clock fanout buffers having a high driving capability, may be connected to the clock signal jitter can not ignore the global clock network meter. BUFG component may be applied to a typical high fan-out signals and the network, such as a reset signal and the clock enable signal. To achieve PLL or the like DCM clock management of global clock, manually embodiment of the buffer.

 

1.1.2 BUFGMUX

 

 

 

 

1.2 I / O port assembly

I / O components provide:

• Local clock buffer;
• Standard single-ended I / O buffer;
• Differential I / O buffer signal;
• DDR dedicated I / O signal buffer;
• Variable tap delay chain;
• pull up;
• drop down;
• Single-ended and differential signals interchangeable;

Primitive	description
BUFIO	I / O cache local clock
DCIRESER	After the FPGA configuration is successful, DCI state machine reset signal
IBUF	Standard capacity and optional I / O single-ended input buffer
IBUFDS	Differential signal input buffer with selectable port
IBUFG	Optionally with dedicated input buffer port
IBUFGDS	Specific differential signal input buffer with selectable port
IDDR	A dedicated input register receiving an input signal, external DDR
Fidel	Dedicated input variable tap delay chain
IDELAYCTRL	IDELAY tap number control module
IOBUF	Port with optional two-way cache
IOBUFDS	Tristate differential output active low signal I / O buffer
ISERDES	Dedicated I / O input buffer resolver
KEEPER	KEEPER Symbol
OBUF	Single-ended output port buffer
OBUFT	Tri-state active low output ports with selectable output buffer
OBUFDS	Differential signal output buffer with selectable port
OBUFTDS	Three-state output buffer with the differential active low selectable output ports
Odd	Dedicated output register for transmitting a signal to the external DDR
OSERDES	For fast implementation the input source synchronous interfaces
PULLDOWN	Input of the register is pulled down to 0
PULLUP	Pulled up to Vcc the input of the register, and the three output ports open

1.2.1 BUFIO

 

1.2.2 IBUFDS