All Xilinx 7 series FPGAs have a built-in ADC called XADC. This XADC has two 1mbps ADCs inside, which can collect analog signals and convert them into digital signals for internal use in FPGA.
XADC can directly obtain chip junction temperature and several power supply voltages of FPGA (7 series does not include VCCO), which is used to monitor the internal status of FPGA. At the same time, 17 pairs of differential pins are provided, one pair of dedicated analog differential inputs, and 16 pairs of multiplexed analog differential inputs, which can be used as ordinary User I/O when not in use.
01
XADC Pinout Requirements module pin requirements:
All the dedicated pins of the XADC module belong to Bank0, so the suffix _0 is added. The above figure 1-2 shows the basic input and output requirements of the XADC: there are two configuration requirements above, and Vccaux (1.8V) is used on the left. Power supply, and use an external 1.25V reference source, use an external reference source to get better performance in terms of accuracy and thermal drift, and use a magnetic bead to isolate the analog ground and digital ground to avoid analog and digital common ground The noise is brought into the analog circuit; the reference source on the chip is used on the right. At this time, the VREFP pin must be connected to the ground as shown in the figure. The following table lists the pin information of the XADC Package:
Note: The XADC module has a dedicated analog channel input pin (VP/VN) that supports differential input, and there are up to 16 auxiliary analog channel input pins (ADxP or ADxN, x is 0 to 15), Kintex-7 Auxiliary channels 6, 7, 13, 14, 15 are not supported. The Zynq-7000 AP SoC device may not support all auxiliary channels due to unsuitable packaging, please refer to the packaging file for details.
02 Operation mode of XADC module
Single channel mode, in this mode, the user must select a channel to be sampled by writing the CH4 to CH0 bits of the control register 40H. In addition, the BU (analog input mode) and ACQ (settling time) parameters of the control register 40H must also be set.
Independent ADC mode, in this mode, ADC A is fixed to implement a "monitoring mode" similar to the default mode, the alarm output function is valid, the user must set the correct alarm threshold; ADC B can only be used Measure external analog input.
Single Pass mode, in this mode, the ADC is stopped after sampling one time sequentially according to the sampling sequence selected by the user. The sample order sequence is set by the user writing sequence channel select registers 48H and 49H.
Continuous Sequence Continuous sequence mode, this mode is very similar to Single Pass mode, the difference is that the system automatically restarts the sequence sampling after one pass of sampling, so it is continuous sampling.
The mode selection is determined by the SEQ3 to SEQ0 bits of the control register 41H, as shown in the following figure:
03 IP core settings
Basic settings
Regarding the specific structure, function and meaning of each parameter of XADC, it should be noted that:
1. The setting of the reference voltage will affect the calculation formula of the error range and sampling value.
2. The analog differential input has requirements on the amplitude of the analog signal, which requires a certain degree of conversion by the external analog circuit.
Assuming that XADC needs to be used to obtain information of several analog signals, how should it be operated. One setting method is explained below.
Note the points in the red box:
1. Use the DRP port to get the digital signal, so the control seems to be simpler.
2. Using the continuous sampling mode, the ADC has been working in the data acquisition mode, and can output after acquisition.
3. Using the Channel Sequencer mode, since there are only two XADCs and too much data needs to be sampled, let the XADCs sample one after another.
4. Set the clock frequency of the DRP port, 50 or 100M is fine, no special requirements.
ADC Setup settings
The second page of IP settings is mainly to set Calibration, average value and external MUX. These few can be skipped for the time being, and you can get an in-depth understanding after you are familiar with the use of XADC.
Alarms settings
The third page sets the alarm parameters, which can not be used. If needed, it can be set up for ease of use.
channel settings
The fourth page sets the channels to be used, here select the temperature and three supply voltages, and select a dedicated analog input channel and the first three multiplexed analog input channels.
The last page is Summary, you can see if there is any problem with the settings, there is nothing to set.
At this time, the most basic XADC for multi-channel data acquisition is set up. As for the settings that are not detailed, you can study after you are proficient in use to find out the most suitable use mode.
04
Port instantiation
Here's how to use this generated IP. Since the DRP port is used to read data, a DRP read-write controller needs to be designed. However, since the XADC itself provides some signals, the design is actually very simple.
The remaining four DRP ports, two outputs and two inputs. The two outputs are directly drawn out, among which do_out is the final required data. This port is 16bit, just take the high 12bit (corresponding to the 12bit declared in XADC).
There are two more IP ports of XADC named eoc_out and channel_out. Connect eoc_out to the den_in port of the DRP port, which means that when one of the multi-channel sampling completes sampling, the DRP port operation is started to start reading data. Add two bits to channel_out and send it to daddr_in as the address signal for DRP port operation. This completes the read and write operations of the DRP.
However, the data output in this way will periodically change among several port data. Therefore, a filtering setting is usually added at the back end. The specific behavior is that when the drdy_out representing the completion of the DRP operation is pulled high, it is judged which channel it is based on the value of channel_out.
For the specific address of each sampling channel, please refer to the manual:
The temperature conversion formula and curve are shown in the figure below:
The voltage conversion formula and change curve are shown in the figure below:
As for the analog differential input pin, it can be directly sent to the corresponding pin on the top layer. Note that the Vivado tool may need to constrain the level of the multiplexed analog pins, and select the corresponding lvcmos according to the voltage value of the VCCO. For example, for a 1.8V VCCO, select lvcmos18.
In this way, the corresponding analog sampling data can be obtained. Since the analog signal to be detected changes relatively slowly in most cases, the use of XADC is sufficient for detection.
There is also MIG IP related to the use of XADC. MIG is the IP of Memory Interface, that is, DDR memory IP such as DDR3. Since the rate of this type of interface is generally too high, temperature information is required to correct the interface. In the configuration of MIG IP, XADC is enabled by default.
At this time, the XADC only needs to provide temperature information. When more information needs to be provided, XADC needs to be configured independently, so that two XADCs will be generated in the project; or two MIG IPs will be instantiated, so that each will require one XADC. Since there is only one XADC module in the hardware, when multiple XADC modules are found in the project, the tool will prompt an error.
The solution is also very simple, remove XADC from MIG IP. Then instantiate the XADC IP independently in the design. Get the temperature information according to the above method and send it to MIG. After MIG IP removes XADC, a temperature port will be generated to receive data. This way there will be no conflicts.
Another very convenient solution to obtain temperature information is to use Hardware Manager. You can see the temperature information by opening XADC in Hardware Manager.
In fact, all channel data of XADC can be obtained through this method.
You can see the interface temperature information Temp 60.3°C in the above figure.