Praise Xilinx SDAccel: Bring FPGA development into the software-defined era
Yang Dong FPGA Development Circle 
Author: Yang
As we all know, Xilinx is the leader of FPGA chip manufacturers. Now it has been established for 30 years, providing us electronic developers with many excellent iterative products, and at the same time continuously optimizing FPGA development tool software. However, with the advent of the Internet era, the scalability and high performance of FPGAs allows them to show their talents in many fields. For example, commercial giants such as Intel and Baidu have begun to use FPGAs as their data centers and use FPGAs to achieve some depth. Learning, artificial neural network algorithms, etc.
Six years ago, Xilinx started a research project that broke the traditional FPGA development process and enabled a set of software development processes to be transplanted to FPGA development. Now the SDAccel development environment has finally met with you. As a member of the Xilinx SDx ecosystem, SDAccel is the first compiler optimized for OpenCL, C and C++ architecture, enabling developers to achieve a CPU/GPU-like development experience on FPGA, such as compilation, debugging and optimization For example, compared to the CPU/GPU unit power consumption performance of the FPGA data center acceleration service implemented by it, the performance of the unit power consumption is increased by 25 times, and the delay is shortened by 50 to 70 times.
Xilinx launches SDAccel: breaking tradition
The following Baidu company announced the results of a survey at the 2014 Hot Chip Seminar:
- The mid-range FPGA can achieve 375 GFLOPS performance with a power consumption of only 10-20W.
- FPGA-based accelerators can be deployed in all types of servers.
- Compared with CPU and GPU, FPGA has better performance in deep neural network (DNN) prediction system. DNN systems are used in various applications such as language recognition, image search, OCR, facial recognition, web search, and natural language processing.
Traditional FPGA development and design use Verilog language to implement RTL design. This kind of development and design cycle is long, and the verilog implementation of some algorithms is more obscure than software programming languages. With the help of some software libraries, we can easily realize our ideas and speed up product development. During the R&D cycle, the SDAccel development environment allows software engineers without FPGA development experience to benefit from the advantages of the FPGA platform.
SDAccel FPGA soft development in three steps
Figure 1 SDAccel development environment
Compile:
In the software development process, compiling the code is the first stage, and the compilation result of the code and the usage rules of CPU/GPU resources are generally fixed. Program developers only need to care about the specific implementation of the algorithm. The FPGA compilation process is a big problem: how to implement the compilation results in the programmable logic resources of the FPGA and the storage method of the FPGA program code.
SDAccel solves these problems. It can identify the logic resources and internal storage structure types of the selected FPGA model. The compiler can extract parallel statements between different states and use the automatic memory structure based on the array read and write method to complete the entire FPGA code. Compilation process.
debugging:
In the software development process, the completion of the compilation process does not mean that the application is developed correctly. We also need to continuously debug on the target hardware to find the problem and correct the error. The software debugging is a very easy to understand problem, but the FPGA needs to be debugged. It is another matter. In order to realize the FPGA debugging function, SDAccel quoted printf and GBD which are often used in software debugging.
The FPGA implementation of Printf wastes some logic resources, which could be used to implement some algorithm functions, but here SDAccel has made some improvements and optimizations to separate the printf data generation from the decoding display. From the hardware point of view, the generation The printf data only needs to consume very few logic resources, and the data decoding and display are completely completed by the upper computer. In this way, the realization of the printf function is almost zero loss of FPGA logic resources.
Program developers can use SDAccel's simulation mode to enter the online simulation function, and can set breakpoints, single-step debugging and other operations like software debugging.
optimization:
The optimization criteria for FPGA applications are the same as the optimization criteria on the CPU, but the implementation method is different. The optimization on the CPU is to focus on the cache size and the number of arithmetic units to be processed, while the application optimization on the FPGA is concerned with the logic of the selected device model. Resources and runtime performance.
Summary outlook
SDAccel launched by Xilinx allows us to see a new form of FPGA development, allowing us to complete the development of FPGA applications like software, compiling, debugging, optimizing and improving the operation process. Xilinx's continuous innovation in recent years has brought about some traditional changes in the industry, such as the recently proposed All Programmable concept and SDx development ecosystem. At the same time, it is no longer a traditional programmable logic company. These innovations not only allow FPGAs to be applied to more fields, but also herald the arrival of a new era—the software-defined era. All we can do is to keep learning and keep up with the times.