FPGA ISP Xilinx MIPI
I prefer Xilinx stuff at home, here to talk about Xilinx home MIPI program. Here ordinary 7 series as an object of discussion, X high-end home KU + / MPSOC + have been directly support the MIPI IO interface.
Because of the rather special MIPI signal, early in the design should take full account of the low power consumption, the signal level of support MIPI native HS and LP modes work in different levels of criteria:
Can be clearly seen from the figure, there are simultaneously present two-level mode MIPI electrical signal, if received on pins of FPGA, obviously it can not be supported by the FPGA.
Meanwhile, HS mode of the standard FPGA level is not supported. Therefore, given the Xilinx home two kinds of programs, implement MIPI signal level conversion, is described in detail in this document XAPP894, the following part is given only MIPI DPHY Rx
A resistor network
At higher line speed MIPI not advisable to use this mode.
2 external chip MC20901
When receiving a camera, only need to use the MC20901
About the MIPI debug
MIPI debug premise is that you correctly complete sensor configuration is recommended from the Internet or FAE Obtain a set of configuration has been proven to drive the sensor. The next focus of this debugging can be put MIPI part. (Supplementary say, high school biology I remember most is a concept: to do experiments on variable control, comparative tests in order to meet the repeated description of a single variable, however ask to mention work, often out of the question raised is positioned wild guess)
As the four Xilinx used MIPI RX Subsystem IP solution, so some users can configure is not much. But this is actually two internal Subsystem IP configuration, one MIPI-DPHY, MIPI-CSI2 is a further interface, and then using the PPI interface between two IP network.
MIPI DPHY by receiving the bit stream data, according to the frame format and then to recover the packet. Packet protocol for ECC check carried out, have a certain ability to identify and correct errors. But if the signal quality is not good, more errors occur, an error is unrecoverable, the image is displayed on the right leads to the fly line o'clock, and even video.
After the completion of a comprehensive, integrated view of the principle of open, enter the MIPI DPHY part, be mark_debug physical layer signal err suffix, and then saved to a file for later xdc debugging
Can be seen from the figure xilinx of MIPI IP PPI interface errorths signal high, indicating the presence of line loss, the situation occurred, if the physical layer error signal constantly, and then checked the FPGA project itself is no problem, you can from the hardware side consider whether there is a problem.
As a MIPI high-speed signal, unfortunately, high-speed oscilloscope and probe not every company has the ...
So, to paraphrase the beloved ginger total sentence: hardware is not strong, the earth was moving ...
