Xilinx-7 Series FPGA---->Spartan-7---->General Logic
----> cheap/low power consumption
---->High I/O port performance
----> Small package
---->Artix-7---->Added PCIE interface
---->Added Gigabit transceiver interface
----> Greater logic density
---->Kintex-7---->PCIE interface
----> DSP Slices are upgraded to DSP48 Slices
----> GTP is upgraded to GTX, the speed is faster
----> Greater logic density
---->Virtex-7---->Enhanced PCIE function
---->Enhanced GTP function
----> Greater logic density
Comparison of the number of DSPs:
Comparison of BRAM quantity:
Comparison of high-speed serial transceivers:
High-speed serial transceiver total bandwidth comparison:
Comparison of I/O number and bandwidth:
Features of Xilinx 7-Series---->28nm process
---->I/O bandwidth: 2.9Tb/s
---->Logic Cell Capacity: 2,000,000
---->DSP operation speed: 5.3TMAC/s
----> Low power consumption
----> True 6-input LUT for distributed storage
---->36Kb dual port BRAM, embedded FIFO logic and on-chip data buffer
---->SelectI/O process, support DDR3 interface, the rate can reach 1866Mb per second
----> High-speed serial connection, rate from 6.6Gb/s to 28.05Gb/s, support low power consumption mode, optimized chip-to-chip interface
----> User configurable analog interface, dual 12-bit 1 MSPS (Million Samples per Second), on-chip temperature/power sensor
---->DSP slices---->25×18 multiplier
---->48bit accumulator
---->High performance filter
---->Optimized equalization coefficient filter
---->CMT---->PLL
---->MMCM (Mixed Mode Clock Management)
---->MicroBlaze CPU---->Integer computing capacity 260 DMIPs~441 DMIPs
----> Integrated PCIe, x4 Gen2~x8 Gen3, suitable for PCIe endpoint/root port design
----> Memory 256-bit AES encryption, HMAC/SHA-256 verification, embedded SEU detection and error checking
---->Environmental protection and high performance
---->1.0V/0.9V core voltage
The following table more intuitively shows the difference between several categories:
Some concepts:
---->SSI Process---->Multiple Super Logic Domain SLRs are used ---->Super High Bandwidth Connectivity
----> low latency
----> Low power consumption
---->Two types---->Logic Enhanced---->Virtex-7T
---->DSP/BRAM/Transceiver Intensive---->Virtex-7XT/HT
----> High volume/high performance/short cycle/low risk
---->Super long routing resources/Super high performance clock lines
---->CLBs---->True 6-input LUT---->Can be configured as a 6-input single-output LUT/64-bit ROM
----> 2 5-input LUTs/32-bit ROMs ----> each with one output
----> Common address and logic input
----> Each LUT output can be optionally connected to a flip-flop
---->4 LUTs+8 flip-flops+multiplexer+arithmetic carry logic---->Slice
---->2 Slices---->CLB
----> 4 of 8 flip-flops (one per Slice, one per LUT) ----> latch latch
----> LUTs can be used as memory ----> 25%~50% of all slices use their LUTs as 64-bit distributed RAM
----> LUTs can be used as registers and shift registers ----> 25%~50% of all slices use their LUTs as 32-bit shift registers SRL32 or 2 SRL16
----> Clock Management ----> Cache and Routing
----> Low jitter
----> Frequency Synthesis and Phase Shift
----> Low jitter clock generator
----> Filter
----> Up to 24 Clock Management Channels CMTs ----> MMCM ----> Fractional Counter
----> Fixed or dynamic phase shift
---->PLL
----> Frequency Synthesizer
----> Clock jitter filtering
---->There is a VCO in the center---->The frequency is related to the voltage passed from the PFD to the VCO
---->3 programmable frequency dividers---->D---->input prescaler
---->M---->Feedback crossover
---->O---->Output frequency division
----> 3 input jitter filtering options ----> low bandwidth ----> best jitter attenuation
----> High Bandwidth ----> Best Phase Offset
---->Optimization mode---->Both balance
---->Clock distribution---->6 different clock lines---->BUFG/BUFR/BUFIO/BUFH/BUFMR/high performance clock
----> Global Clocks ----> 32 Global Clocks
----> can be used as clock for all flip-flops
----> with enable/set/reset
----> 12 clock lines driven by BUGH, which can be driven in any clock domain
----> Each BUFH can be independently enabled and controlled, so the clock can be turned off in one domain
----> Can be driven by global clock buffer ----> glitch-free clock distribution and global clock enable
----> Driven by CMT ----> Eliminate clock distribution delay
---->Domain Clock---->Drives all clock targets in the domain
----> Domain definition refers to the range of 50 I/O and 50 CLB and half chip width
---->7 series can have 2~24 domains
----> Each domain has 4 domain clock paths
----> The domain clock buffer is driven by 4 clock input pins and can be divided by 1~8 at the same time
---->I/O Clock---->Fast
----> as I/O logic or serialization/deserialization circuit
---->I/O can be directly connected to MMCM
---->Block RAM---->Dual port, 72-bit, 36kb BRAM
----> Programmable FIFO logic
---->Error checking circuit
----> 5 to 1880
----> Read and write synchronous operation
----> Programmable data bit width
---->DSP Slice----> 25 × 18 Two Complementary Multiplier Adder 48-bit High Resolution Single Multiplier Adder
---->Single instruction multiple data arithmetic unit SIMD/2 operand 10 logic units with different logic functions
----> Power saving pre-adder
----> Equalization Filter
---->Pipeline/ALU/dedicated bus cascade
---->up to 741MHz
----> 48-bit pattern detector
---->High speed/high efficiency
----> Dynamic Bus Converter
----> Memory Address Generator
---->Bus Multiplexer
---->I/O port memory map register
---->The accumulator can be used as a synchronous up-down counter
---->Input and output---->SelectIO process
---->1,866Mb/s DDR3 interface
----> On-chip high-frequency decoupling capacitors enhance signal integrity
----> Supports multiple I/O standards
---->HR IO---->Wide voltage range (1.2V~3.3V)
---->HP IO---->High Performance Operation
---->Organized by Bank, 50 pins per Bank
----> Each Bank is jointly powered by VCCO
----> Some single-ended input buffers require an external reference voltage VREF
----> There are 2 VREF pins per Bank (except for configuration Bank 0) ----> There can only be one VREF voltage value
---->Various packages
---->Electrical characteristics---->Up and down output structure
----> can be set to high impedance state
----> Slew rate and output strength can be set
----> Pull-up and pull-down resistors can be set
----> Pin pair can be set as differential input and output
----> 100 ohm internal termination resistance can be set
---->Various differential interface standards: LVDS, RSDS, BLVDS, differential SSTL, differential HSTL
---->Each IO port supports memory interface standard
---->T_DCI can control the output drive impedance ---->Series termination/parallel short
----> Save board space
----> Output mode or tri-state mode termination will automatically turn off
---->IBUF and IDELAY have low power mode
----> 8-bit IOSERDES can complete serial-parallel and parallel-serial conversion ----> programmable width 2 to 8 bits
----> Support adjacent pins cascade
----> Dedicated oversampling mode for data recovery ----> such as SGMII interface
----> Low Power Gigabit Transceivers
---->Integrated PCIE interface
----> Configuration
----> Analog to digital conversion