Reference: http://www.zynqbook.com/
ZYNQ architecture
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Dual-core ARM Cortex-A9 processor: ARM Cortex-A9 is an application-level processor that can run a complete operating system like Linux
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Conventional field programmable gate array (Field Programmable Gate Array, FPGA) logic means: based Xilinx 7 Series FPGA architecture
This architecture implements the industry-standard AXI interface, and achieves a high-bandwidth, low-latency connection between the two parts of the chip.
This means that the processor and the logic part can be used to their best use, without the kind of interface overhead between two separate chips.
Peripherals are functional components other than the processor, and generally perform one of three functions: (1) Coprocessor-a unit that assists the main processor, which is often optimized for specific tasks; (2) Interaction with external interfaces The core, such as connecting to LEDs and switches, codecs, etc.; (three) additional memory units.
PS has a fixed architecture that carries the processor and system storage area
The PL is completely flexible , giving designers a "blank canvas" to create customized peripherals or reuse standard peripherals.
ZYNQ's basic model of SoC design flow
ZYNQ chip
Processor system (PS)
ARM is a "hard" processor, another solution besides the hardware processor, like a "soft" processor like Xilinx's MicroBlaze, which is a combination of programmable logic units. In other words, the implementation of a soft processor is equivalent to any other IP package deployed in the logic structure of the FPGA. Less demanding tasks can be separated from the main ARM Cortex-A9 processor and assigned to the soft processor. The soft processor and ARM work together to improve overall performance
PS is not only the ARM processor, but also a set of related processing resources, forming an Application Processing Unit (APU) , in addition to the extended peripheral interface, cache memory, memory interface, interconnection interface and clock generation Circuit
The external interface of the processor system-the communication between the PS and the external interface is mainly achieved through multiplexed input/output (MIO). Such a connection can also be realized by extending EMIO (ExtendedMIO, EMIO). EMIO is not a direct path between PS and external connections, but is realized by sharing I/O resources of PL.
Available I/O includes standard communication interfaces (SPI, I2C, USB, SD, CAN, UART, GigE) and general purpose input/output (General Purpose Input/Output, GPIO)
Programmable logic (PL)
LUT-lookup table
FF-flip-flop, a sequential circuit that realizes 1-bit register, with reset function. One use of FF is to achieve latching.
CLB-configurable programming logic block
IOB-Input/Output Blocks (IOB)-realizes the connection between PL logic resources and provides physical device "pads" to connect external circuits. Each IOB can handle one bit of input or output signal. IOB is usually located on the periphery of the chip.
In addition to the general part, there are two special-purpose components: block RAM to meet the needs of dense storage and DSP48E1 chip for high-speed arithmetic
General-purpose input and output IOB
Communication interface-including PCIExpress, Serial RapidIO, SCSI and SATA
Other programmable logic extension interfaces--XADC, clock, programming and debugging
Interface of processor system and programmable logic
1. AXI standard--Advanced eXtensible Interface
There are three types of AXI4 bus protocol
• AXI4 [2] — used for memory mapping links, it supports the highest performance: an address is given by a cluster of up to 256 data words (or "data beats") data transmission.
• AXI4-Lite [2] — A simplified link that only supports one data per connection (not batch). AXI4-Lite is also memory mapped: under this protocol, one address and single data are transmitted at a time.
• AXI4-Stream [1] — Used for high-speed streaming data, supporting batch transmission of unlimited size data. There is no address mechanism, this bus type is best suited for direct data flow between source and destination (not memory mapped)
Interconnect : Interconnect is actually a switch that manages and directly transfers the communication between the connected AXI interfaces. There are several interconnections in the PS, some of which are directly connected to the PL (Figure 2.9), while others are only used for internal connections. The connections between these interconnections are also made up of AXI interfaces.
Interface : A point-to-point connection used to transfer data, address and handshake signals between the host and slave in the system. (M-Master, S-Slave)
• General Purpose AXI (General Purpose AXI) — a 32-bit data bus suitable for medium and low speed communication between PL and PS. The interface is transparent without buffering. There are a total of four general interfaces: two PS as the host, and the other two PL as the host.
• Accelerator Coherency Port—A single asynchronous connection between the PL and the SCU in the APU, with a bus width of 64 bits. This port is used to achieve the consistency between the APU cache and the PL unit. PL is the host.
• High Performance Ports — Four high-performance AXI interfaces with FIFO buffers to provide "bulk" read and write operations, and support high-speed communication of memory cells in PL and PS. The data width is 32 or 64 bits, and the PL is the host in all four interfaces.
2. EMIO interface
3. Other PL-PS signals
Other signals that cross the PS-PL boundary include watchdog timers, restart signals, interrupts, and DMA interface signals.
to sum up
Multiplexed I/O (MIO): PS peripheral IO multiplexing, what is this concept? The previous introduction of ZYNQ is mainly divided into two major components: PS/PL. The peripherals introduced on the PS side, such as USB/CAN/GPIO/UART, need pins to interact with the outside world. The so-called multiplexing here is related to common single-chip microcomputers and processing. The concept of pin multiplexing in the device is the same. But (the key point here), ZYNQ has up to 54 PS pins to support MIO, MIO has very high flexibility to achieve flexible configuration, which brings great convenience to hardware design and PCB layout! , MIO configuration can be flexibly configured using vivado software.
Hardware engineers often find that the layout of a complex system is often difficult, and they often fall into EMC pits because of unreasonable layouts. ZYNQ's IO pins are highly flexible, which undoubtedly provides great convenience in circuit design and can realize very flexible PCB layout and routing. This brings great convenience in EMC performance improvement.