Chapter 1 Overview of EDA Technology
Digital devices have gone from SSI, MSI, LSI to VLSI, until now SoC (System on Ship, chip system).
SSI: small scale integrated circuit
MSI: medium scale integrated circuit
LSI: large scale integrated circuit
VLSI: very large scale integrated circuit
PAL: programmable logic array
GAL: general array logic
PCB: printed circuit board
FPGA: field programmable gate array
CPLD: complex programmable logic device
CAD: Computer Aided Design
CAE: Computer Aided Engineering
EDA: Electronic Design Automation
RTL: Register Transfer Level
HDL: hardware description language
ASIC: application specific integrated circuit
SoPC: programmable chip system
DSP: digital signal processing
1.1 Top-down design
Top-down design is a top-down design. Divide and structure the functional block diagram on the top layer to avoid the waste of design work, reduce the workload, and increase the success rate.
During the design process, multiple simulations and verifications are required to continuously modify the design.
1.2 Botton-up design
Botton-up design is a bottom-up design. Call the basic unit and combine it step by step until a system that meets the requirements is designed, which is inefficient and error-prone.
1.3 IP core is divided into hard core, solid core and soft core.
IP core: a circuit function module with a pre-designed number used in ASIC or FPGA.
Soft core: used in Verilog HDL and other hardware description language function modules, but does not involve any specific circuit components to achieve these functions.
Hardcore: Provide the final product at the design stage.
Solid core: completed a comprehensive function block.
1.4 Digital design process
Design input-> synthesis-> place and route-> simulation-> programming configuration
synthesis: the process of automatically converting the design description at a higher level of abstraction into a lower level description.
The essential difference between a hardware synthesizer and a software compiler: program code written in a hardware description language generates a circuit netlist structure; and a software compiler generates CPU instruction / data code streams.
1.5 Placement and wiring: also known as adaptation
1.6 Programming configuration
The downloading of CPLD devices based on the non-volatile structure of the EEPROM process is generally called programming, and the downloading of FPGA devices based on the SRAM process structure is called the configuration.
1.7 Common EDA tool software
1) Integrated FPGA / CPLD development tools
Intel (Altera): Max + Plus II, Quartus II, Quartus prime;
Xilinx: ISE, Vivado;
Lattice: ispLEVER, Classic, Diamond
2) Logic synthesizer
Synopsys: FPGA Express, FPGA Compiler and FPGA Compiler II;
Synplicity: Synpify Pro / Synoplify;
Mentor: Leonardo Spectrum.
... (simulation tools, comprehensive tools)
Chapter 2 FPGA / CPLD devices
2.1 Overview of
PLD devices 2.1.1 Classification of PLD devices
1) Classification by integration level
Simple PLD (SPLD) <-750—> High density PLD (HDPLD)
Simple programmable logic device (SPLD)
SPLD includes PROM, PLA, PAL, and GAL;
PROM: programmable read-only memory
PLA: programmable logic array
PAL: programmable array logic
GAL: general programmable array logic
High-density programmable logic device (HDPLD)
HDPLD includes CPLD, FPGA;
2) Classification according to programming characteristics
According to the programming times:
One-time programming device (OTP)
can program the device multiple times
The characteristics of OTP devices are: only allow the device to be programmed once, and cannot be modified; while the multiple-programmable device allows multiple programming, which is suitable for use in scientific research and development.
According to different programming elements and programming processes
A device using a fuse_program element.
Device
using antifuse (Antifuse) programming element Device using ultraviolet erasure and electrical programming
EEPROM type
Flash memory (Flash) type
Structure device using static memory (SRAM)
The first five types of programming process structure devices are called non-volatile devices, and the last type is volatile devices.
3) Classification according to structural characteristics
PLD device
based on multiplication term structure PLD device based on lookup table structure
2.2 The principle and structure of low-density PLD
1) PROM has
low defect utilization rate, fixed and array, programmable (or array) gate array;
2) PLA has
high utilization rate, saves chip area, disadvantages, software development is difficult, and algorithm is complex .
Programmable and array, or array (programmable)
3) PAL
and array can be realized, or the array is fixed
4) GAL
2.3CPLD
CPLD is and or array structure.
2.4 The principle and structure of
FPGA FPGA is a lookup table structure
The similarities and differences between CPLD and FPGA
CPLD is an AND or array structure (macrocell), which is a programmable logic device. It can be defined by the user according to his needs after the manufacturing is completed.
FPGA is a look-up table structure, which solves the shortcomings of customized circuits and overcomes the shortcomings of the original programmable device gate circuit.
2.5 Boundary Scan Test Technology
VLSI: Very Large Scale Integrated Circuit
JTAG: Joint Test Action Group
BST: Boundary Scan Test
2.6 Programming and Configuration of FPGA / CPLD
ISP: In-System Programmable
Chapter 3 Preliminary Verilog Design
verilog template:
module <顶层模块名>(<输入输出端口列表>);
input 输入端口列表; //输入端口声明
ouput 输出端口列表; //输出端口声明
/*定义数据，信号的类型，函数声明，用关键字定义*/
wire 信号名;
reg 信号名;
//逻辑功能定义
assign <结果信号名>=<表达式>;
//用always块描述逻辑功能
always @(<敏感信号表达式>)
begin
//过程赋值
//if-else，case语句
end
endmodule
Voter function:
module voter(pass,vote);
input [6:0]vote;
output pass;
reg[2:0] sum;integer i;reg pass;
always @(vote)
begin sum=0;
for(i=0;i<=6;i=i+1)
if(vote[i])sum=sum+1;
if(sum[2])pass=1;
else pass=0;
end
endmodule
Realizing two 8-bit multipliers with for statement
module mult_for(a,b,outcome);
parameter size=8;
input [size-1:0] a,b;
output reg [2*size-1:0] outcome;
integer i;
always @(a or b)
begin
outcome<=0;
for(i=1;i<=2*size；i=i+1)
outcome<=outcome+(a<<(i-1));
end
endmodule
Use repeat to multiply two 8-bit binary numbers.
module mult_repeat
#(parameter size=8)
(input [size-1:0] a,b,output reg [2*size-1:0] result);
reg [2*size-1:0] temp_a;reg [size-1:0]temp_b;
always @ (a or b)
begin
result =0;temp_a=a;temp_b=b;
repeat(size)
begin
if (temp_b[1])
result=result+temp_a;
temp_a=temp_a<<1;
temp_b=temp_b>>1;
end
end
endmodule
Adder:
module adder(cin,a,b,sum,cout);
input cin;
input [7:0] a,b;
output [7:0] sum;
ouput cout;
assign {cout,sum}=a+b+cin;
endmodule
An adder:
module add(a,b,cin,sum,cout);
input a,b,cin;
output sum,cout;
always @*
begin
{cout,sum}=a+b+cin;
end
endmodule
always can also be used in combination circuits!
The always procedure statement usually has a trigger condition. The trigger is written in the sensitive signal expression. Only when the trigger condition is met, subsequent statements can be executed.
Talking about the circuit, you have to talk about the difference between reg and wire variables?
Wire is a commonly used net-type data variable. Net-type data is equivalent to various physical connections in hardware circuits. Simply put, wire is equivalent to a wire, which is commonly used in a combination circuit. The reg type variable belongs to the variable type variable and must be placed in the process statement. The value is assigned through the process assignment statement, which is common in registers and sequential circuits.
Chapter 4 Language Elements
Just read the program, what bicycle do you want?
- Blank characters, program decoration, as beautiful as possible
- Comment, not much to say like C /// and / * * /
- Identifier, a little bit different, can exist in $, I haven't seen it in C
- Keywords, what you see
- Operators, in mathematics, in C
constant
· Integer +/- <size> '<base> <value>
· Real number
· String
4.1
· Binary (b / B)
· Octal (o / O)
· Decimal (d / D)
· Hexadecimal (h / H)
Example: 8'b11000101, eight-bit wide binary
is allowed between base and value There are spaces, but no spaces between 'and hexadecimal, and values.
4.2 Values
: 0: low level, logic 0 or logic not
• 1: high level, logic 1 or “true”
• z / Z: high resistance state
• x / X: unknown state
4.3 Parameter
Chapter 5 Verilog statement syntax
What grammar is required, can use the
case statement to describe the 4 select 1 data selector
module mux4_1(out,in0,in1,in2,in3,sel);
input in0,in1,in2,in3;
input [1:0] sel;
ouput reg out;
always @ (in0 or in1 or in2 or in3 or sel)
case(sel)
2'b00:out=in0;
2'b01:out=in1;
2'b10:out=in2;
2'b11:out=in3;
default:out=2'bx;
endcase
end
endmodule
BCD code-7 segment code tube decoder
module decode7(D,a,b,c,d,e,f,g);
input [3:0] D;
output reg a,b,c,d,e,f,g;
always @*
begin
case(D)
4'd0:{a,b,c,d,e,f,g}=7'b1111_110;
4'd1:{a,b,c,d,e,f,g}=7'b0110_000;
4'd2:{a,b,c,d,e,f,g}=7'b1101_101;
4'd3:{a,b,c,d,e,f,g}=7'b1111_001;
4'd4:{a,b,c,d,e,f,g}=7'b0110_011;
4'd5:{a,b,c,d,e,f,g}=7'b0110_011;
4'd6:{a,b,c,d,e,f,g}=7'b1011_111;
4'd7:{a,b,c,d,e,f,g}=7'b1110_000;
4'd8:{a,b,c,d,e,f,g}=7'b1111_111;
4'd9:{a,b,c,d,e,f,g}=7'b1111_110;
default:{a,b,c,d,e,f,g}=7'b1111_110;
endcase
end
endmodule
Multiply two 8-digit numbers with for statement
module mult_for(a ,b,outcome);
input [7:0]a,b;
output reg[15:0] outcome;
integer i;
always @(a or b)
begin outcome <=0;
for(i=1;i<=8;i=i+1)
if(b[i]) outcome <=outcome+(a<<(i-1));
end
endmodule
Multiply two 8-bit binary numbers with repeat
module mult_repeat
#(parameter size = 8)
(input [size:1] a,b;
output reg[2*size:1] result);
reg [2*size:] temp_a;reg[size:1] temp_b;
always @)(a or b)
begin
result=0; temp_a=a;temp_b=b;temp_b=b;
always(size)
begin
if(temp_b[1])
result=result+temp_a;
temp_a=temp_a<<1;
temp_b=temp_b>>1;
end
end
endmodule
We are used to multiplying two numbers with a for loop, and for seems to be better understood. When the number on b is 1, then a moves to the left.
Voting device
module voter7(input [6:0] vote,output reg pass);
reg [2:0] sum; integer i;
always @ (vote)
begin sum=0;
for(i=0;i<=6;i=i+1)
if(vote[i]) sum=sum+1;
if(sum[2]) pass=1;
else pass=0;
end
endmodule
