The design of the perpetual calendar is as follows: (using verilog language) suitable for quartusII or vivado
A digital_clock design requirement
This design uses FPGA to achieve core control. Use independent keys as input, and use six-in-one common anode nixie tube as display device. Specific requirements are as follows:
- The digital clock is required to display the time, date, and alarm time. This design uses verilog to achieve core control.
- Use the decimal point to separate the displayed content when displaying. (Example: 19.12.55)
- The keys for external input include the switch key, the adjustment key, the plus key, and the minus key. (The keys are replaced by switches) The specific functions are as follows:
The digital clock is required to display the time, date, and alarm setting time. Use the switch button to perform the year, month, day, time, and alarm timing operations. The three states can be adjusted by adding or subtracting two buttons. For the selected digital tube adjustment position, it flashes to indicate that it has been selected, for example: first switch to the date, select it to indicate "Year" nixie tube, then the selected digit flashes for 0.5 seconds to indicate the selection, and then the number can be increased or decreased through the increase and decrease buttons. In addition, after the key is deviated, each time the key is pressed, the buzzer will sound to indicate that it has been pressed; when the set alarm is up, any key pressed will stop the buzzer, if no key is pressed, the buzzer will sound for a long time After 1min, it will stop automatically.
The top-level design block diagram is as follows: