The basic design concept of the digital frequency counter T is the number of time a given measurement is started when produced, i.e. using a standard reference clock, counts the number of pulses of the measured signal in a unit time (one second) in . Frequency measurement method comprises a direct frequency measurement method, measurement precision frequency, cycle method and the like.
The principle of digital frequency meter shown in Figure 6-1. Generating an output frequency of 1Hz is used as a clock input to the control module, the control module is generated by the count enable signal and a clear signal to the counting module is controlled by the latch signal generated by the load of the system clock signal for dividing latch control module, once the count enable signal is high, and the clock rising edge, the counter starts to count normally, the arrival of the count clear signal is cleared, and when the latch signal is high, and the data is latch latches, then outputs the latched data to the display module is displayed, the system can ensure stable data latch display data, the display driver circuit decodes the counting result into a corresponding binary representation can be displayed on a digital the results can be displayed in decimal.
(1) frequency divider module
Will the system clock divider block dividing, 1Hz Hz output signal as an input signal frequency measurement control module. For example, assume that the system clock is 1024Hz, then subjected to the power of 10 to obtain a frequency divider 2 dividing an output signal of 1Hz.
(2) Frequency Measurement control module
Frequency measurement control module comprises an output enable terminal of the counter, the latch signal and the clear terminal of the data latch. And control the counting of the counter is cleared. When the latch signal is high, the counting result of the counter is latched and output to the display module to display.
View Code
The simulation module may refer to Figure 6-2.
(3) counter module
The counter unit is a complete counting step. It is also used with the frequency, timing and pulse generating beat pulse sequence or the like. This design allows for proper operation, must be 1 when it starts counting only when the enable terminal, the arrival time of each rising edge of the clock counter is incremented to 10 when the accumulated when he is cleared, while generating a carry signal simultaneously with the counter clear signal should, once the clear signal is active, the counter is cleared immediately.
(4) latch block
Latch, the signal is temporarily stored in order to maintain a certain level status. After task success measurement module, the rising edge of the load signal arrival measurements reg into which, after sending them to the display module. Latch is mainly to protect the data, it is still valid in the next trigger or reset.
(5) Display Module
In many digital LED display system as a display output device, it is widely used. It has seven luminescence inside a, b, d, e, f and g diode. By lighting an LED of different fields, different characters may be displayed numbers 0,1, ┅, 9 and A, b, C, d, E, F, etc., and customize some simple symbols representative of the light emitting section.
(6) top-level module
A block diagram of a digital frequency meter shown in FIG accordance call each unit module, complete digital frequency meter top-level design and simulation, frequency measurement.
Exercise
(1) frequency divider module
1 module fre_div (clk, clk_out);
2 input clk;
3 output clk_out;
4 reg [8:0] counter;
5 reg clk_out;
6 parameter N = 1000; //改变N的值变成任意偶分频，同时counter的范围需要相应修改
7
8 always @ (posedge clk)
9 begin
10 if (counter == N/2 - 1) //偶分频数一半时反相
11 begin
12 clk_out <= ~clk_out;
13 counter <= 0; //置0，从0计数
14 end
15 else
16 counter <= counter + 1;
17 end
18 endmodule
(2) Frequency Measurement control module1 module testctl (clk_out_ctl, tsten, rst_ctl, load);
2 input clk_out_ctl;
3 output tsten, rst_ctl, load;
4 reg rst_ctl, div2;
5 always @(posedge clk_out_ctl) begin
6 div2 = ~div2;
7 end
8 always @(clk_out_ctl or div2) begin
9 if (clk_out_ctl == 0 && div2 == 0) begin
10 rst_ctl = 1;
11 end
12 else
13 begin
14 rst_ctl = 0;
15 end
16 end
17 assign load = ~div2;
18 assign tsten = div2;
19 endmodule
(3) counter module ( correction in comments )
1 module counter (enable,clk_t,rst_count,dout,cout);
2 input enable,clk_t,rst_count;
3 output [15:0] dout;
4 output cout;
5 reg cout;
6 reg [15:0] dout;
7 always @(posedge clk_t) begin//有问题，always @(posedge clk_t or posedge rst_count) //异步复位
8 if (!rst_count) begin// if (rst_count) begin dout = 16'd0; cout = 1'b0; end //先写复位，首先考虑复位信号
9 if (enable) begin// else begin
10 if(dout == 65535) begin // if (enable) begin
11 dout = 16'd0; // if(dout == 65535) begin dout = 16'd0; cout = 1'b1; end
12 cout = 1'b1; // else dout = dout + 16'd1;
13 end // end
14 else begin // end
15 dout = dout + 16'd1;
16 end
17 end
18 end
19 else begin
20 dout = 16'd0;
21 cout = 1'b0;
22 end
23 end
24 endmodule
25
26
27
(4) latch block
1 module latch_out (in_dout, save_dout, load_in);
2 input load_in;
3 input [15:0] in_dout;
4 output [15:0] save_dout;
5 reg [15:0] reg_in;
6 wire [15:0] save_dout;
7 always @(load_in)
8 if (load_in)
9 reg_in = in_dout;
10 assign save_dout = reg_in;
11 endmodule
(5) Display Module
[1] BCD binary switch module ( Reference )
1 module bin_bcd_cp (bin, wan, qian, bai, shi, ge, bcd);
2 input [15:0] bin;
3 output [31:0] bcd;
4 output reg [3:0] wan;
5 output reg [3:0] qian;
6 output reg [3:0] bai;
7 output reg [3:0] shi;
8 output reg [3:0] ge;
9 integer i;
10 always @(bin) begin
11 wan = 4'd0;
12 qian = 4'd0;
13 bai = 4'd0;
14 shi = 4'd0;
15 ge = 4'd0;
16 for (i = 15; i >= 0; i = i - 1) begin
17 if (wan > 4) wan = wan + 3;
18 if (qian > 4) qian = qian + 3;
19 if (bai > 4) bai = bai + 3;
20 if (shi > 4) shi = shi + 3;
21 if (ge > 4) ge = ge + 3;
22
23 wan = wan << 1;
24 wan[0] = qian[3];
25 qian = qian << 1;
26 qian[0] = bai[3];
27 bai = bai << 1;
28 bai[0] = shi[3];
29 shi = shi << 1;
30 shi[0] = ge[3];
31 ge = ge << 1;
32 ge[0] = bin[i];
33 end
34 end
35 assign bcd = {{12{1'b0}}, wan, qian, bai, shi, ge};
36 endmodule[2] eight digital tube display
module seg7 (data_in, data_out );
input [3:0] data_in ;
output [7:0] data_out ;
reg [7:0] data_out ;
always @(data_in) begin
data_out = 7'b1111111;
case (data_in )
4'b0000: data_out = 8'b1100_0000; // 0
4'b0001: data_out = 8'b1111_1001; // 1
4'b0010: data_out = 8'b1010_0100; // 2
4'b0011: data_out = 8'b1011_0000; // 3
4'b0100: data_out = 8'b1001_1001; // 4
4'b0101: data_out = 8'b1001_0010; // 5
4'b0110: data_out = 8'b1000_0011; // 6
4'b0111: data_out = 8'b1111_1000; // 7
4'b1000: data_out = 8'b1000_0000; // 8
4'b1001: data_out = 8'b1001_1000; // 9
4'b1010: data_out = 8'b1000_1000; // A
4'b1011: data_out = 8'b1000_0011; // b
4'b1100: data_out = 8'b1010_0111; // c
4'b1101: data_out = 8'b1010_0001; // d
4'b1110: data_out = 8'b1000_0110; // E
4'b1111: data_out = 8'b1000_1110; // F
default: data_out = 8'b1111_1111;
endcase
end
endmodule
(6) top-level module
The module generates each symbol, by creating block diagram schematic file generated manually connect /.
RTL:
Simulation waveforms:
Note: The simulation test various small modules must be done one by one (here I omitted)