Realize verilog design to control traffic lights

This design can be used in vivado or quartusII under the environment of ISB14.7.

The project screenshot and top-level design are as follows:

 

Part of the code of the top-level file of this design is as follows:

`timescale 1ns / 1ps

//The top level file of the traffic light controller
module top(clk,data,seg_cs,seg_scan,row,led_cs);

input clk;
input [1:0] row;
output reg [7:0] data;
output seg_cs;
output [3:0] seg_scan;
output [1:0] led_cs;

//Digital tube display

scan_ctrl scan_ctrl_inst (
    .rst(rst), 
    .clk(clk), 
    .key_cs(key_cs), 
    .seg_cs(seg_cs), 
    .seg_scan(seg_scan),  
    .led_cs1(led_cs1), 
    .led_cs2(led_cs2), 
    .clk_10k_pulse(clk_10k_pulse)
    );

//LED light control module

led_ctrl  led_ctrl_inst(