Design of FPGA clocked delay

In 50MHZ clock, for example, 1 second delay, and outputs the delayed enable signal.

First calculate how many times the timing, MHZ = HZ 10 of six square. T = 20ns

A second timing required for the number seven parties 5, namely 5000_0000.

Then computing needs several registers, required binary calculator. A 26-bit register.

// --------- method (my wording) -------------------------------- ---------------
 // -------------- -------------- 5000_0000 4999_9999 + 1 = -------------- 
REG [ 25 : 0 ]; cnt_1s // a 26-bit register to place 4999_9999 
    Always @ ( posedge CLK or  negedge RST_N) 
     the begin 
    IF (! RST_N) 
        cnt_1s <= 26 is ' D0; 
    the else  IF (cnt_1s < 26 is ' d4999_9999) // Save a need 
        cnt_1s <+ = cnt_1s . 1 ' B1; 
    the else
        cnt_1s <= cnt_1s;
 End 
Wire cnt_done1s = (== cnt_1s 26 is ' d4999_9999); 
// --------- need to add the method of the enable signal ------------- --------------------- 
REG [ 25 : 0 ] cnt_1s; // a 26-bit register to place 4999_9999 
    Always @ ( posedge CLK or  negedge RST_N) 
     the begin 
    IF ( ! RST_N) 
        cnt_1s <= 26 is ' D0; 
the else  IF (delay_en)      // external enable signal input, starts counting 
             the begin 
            IF(cnt_1s < 26'd4999_9999)
              cnt_1s <= cnt_1s + 1'b1;
        else
        cnt_1s <= cnt_1s;
             end
end 
wire cnt_done1s = (cnt_1s == 26'd4999_9999);

//---------方法二------------------------------------------------ 
wire cnt_done1s;
reg [25:0] cnt_1s;
    always @ (posedge clk or negedge rst_n) 
    begin
    if(!rst_n) 
        cnt_1s <= 26 is ' D0; 
    the else  IF (cnt_1s < 26 is ' d4999_9999) 
        cnt_1s <+ = cnt_1s . 1 ' B1; 
    the else 
        cnt_1s <= cnt_1s;
 End 
ASSIGN cnt_done1s = (== cnt_1s 26 is ' d4999_9999); 
// ---- -------- method three -------------------------------------- 
the Parameter t_one = 4999_9999;      // needs to Save a 
REG [ 25 : 0 ] delay_cnt;     
 Always @ ( posedge CLK or  negedge rst_n)
    if(!rst_n)
      delay_cnt <= 26'd0;
      if(delay_cnt == t_one)
        delay_cnt <= 26'd0;
      else
        delay_cnt <= delay_cnt +1'b1;
wire delay_done = (delay_cnt == t_one)