Design level of abstraction
Before we look at the details of the Verilog language, it is best to understand the different levels of abstraction in chip design.
The top level is the system-level architecture, which defines various sub-modules and groups them based on functionality. For example, a processor cluster has multiple cores, caches, and cache coherence logic. All of this will be packaged as a single module with input and output signals.
At the next level, each submodule is written in a hardware description language to accurately describe the functionality of each individual module. At this stage, lower-level implementation details such as circuit schematics, technology libraries, etc. are ignored. For example, a controller module will eventually contain multiple Verilog files, each describing a detailed component that implements its functionality.
The HDL is then converted into a gate-level schematic, which also involves technology libraries that characterize digital components such as flip-flops. For example, the digital circuit of a D latch contains NAND gates arranged in such a way that all combinations of D and E inputs produce the output Q given by the truth table.
The truth table essentially gives the arrangement of all input signal levels and the final output level, the example given below is a D latch with an enable pin. Hardware schematics can also be derived from truth tables using Boolean logic and Karnaugh maps. However, for more complex digital modules such as processors and controllers, using this approach is somewhat impractical.
NAND gates are implemented by connecting CMOS transistors in a specific format. At this level, the transistor channel width, Vdd, and the ability to drive the output capacitive load are considered in the design process.
The final step is to use EDA tools to lay out these transistors in silicon for mass manufacturing. At this level, some equipment and technical knowledge is required because different layouts end up with different physical properties, such as resistance and capacitance, etc.
design style
Secondly, the design of digital modules mainly follows two styles, namely top-down and bottom-up approaches.
top down
In this style, the top-level module is first defined along with the identities of the submodules required to build the top-level module. Similarly, each sub-module will be further divided into smaller components, and the process can continue until it reaches a leaf cell or a stage where no further division is possible.
bottom up
In this case, the first task is to identify the available building blocks. They are then put together and connected in some way to build larger units that can be used to piece together the top modules.
In practice, both processes are usually used. The architect defines a system-level view of the design, and the designer implements the logic of each functional module and synthesizes it into the gate. So far, a top-down style has been followed. However, these gates are built following a bottom-up process, starting with the physical layout of the smallest module for the best possible area, performance, and power consumption. These standard units also feature hardware schematics that can be used to obtain information such as rise and fall times, power and other delays, etc. These units are available to the synthesis tool, which picks them up and instantiates them when needed.