Accurate long delay circuit
The circuit is composed of CD4060 as the time base circuit of the timer, and the timing time base pulse generated by the circuit is divided by the internal frequency divider to output the time base signal. Through the frequency division of the peripheral frequency division circuit, the required timing control time is obtained.
1. The working principle of the circuit
The circuit principle is shown in Figure 13.
After power on, the time base oscillator oscillates and outputs the time base signal after frequency division. IC2 as a frequency divider starts counting frequency division. When the count reaches 10, Q4 outputs a high level, and the high level is turned into a low level by D1 inversion to make VT cut off, the relay is powered off and released, and the working power of the controlled circuit is cut off. At the same time, the low level output by D1 is inverted to high level by D2 and then added to the CP terminal of IC2, so that the high level output at the output terminal remains.
After the circuit is energized to reset IC1 and IC2, the four output terminals of IC2 are all low level. The low level output by Q4 is changed to high level through D1 inversion, and VT is turned on through R4, and the relay is energized and absorbed. This working state is the power-on state and the timed state.
2. Component selection
IC1 uses CD4060, IC2 uses CD4518, IC3 uses CD4069; VT1 uses 9013, 9014; C1 uses ceramic capacitors, C2 and C3 use aluminum electrolytic capacitors with a withstand voltage of 15V; relays use model JZC-6F DC relays ; RP uses 200K ordinary adjustable potentiometer; resistor uses 1/8 or 1/4W metal film resistor, SA1 and SA2 are small toggle switches.
3. Production and debugging method
If you want to change the power-on disconnection and timing status, you can add a one-stage inverter between the output terminal D1 and VT. The length of the timing time can be adjusted through RP, and can also be changed by connecting the output terminal of IC2 according to the corresponding relationship of binary codes. The timing range of the circuit in this example is: 3min~1h.
Digital long delay circuit
General long delay circuits usually use electrolytic capacitors or high impedance circuits. The stability of this kind of delay circuit is poor, and the precision of delay is not high. Here is a digital long-delay circuit, which completely abandons large electrolytic capacitors and high-impedance circuits, and has high delay accuracy.
1. Circuit working principle
The circuit principle is shown in Figure 14.
The core of the circuit is the integrated block MCI4521B, which is a 24-stage frequency division circuit, which contains an inverter that can form an oscillating circuit. If the trigger input terminal is grounded or no signal is added, the circuit enters the delay state, and the delay time is adjusted by the range switch X and the 100KΩ potentiometer.
If X is connected to point A, the time delay is from 1 minute 40 seconds to 18 minutes 30 seconds, and if X is connected to point B, the time delay is from 13 minutes 20 seconds to 2 hours 28 minutes. When X is connected to point C, the time delay is from 1 hour 47 minutes to 20 hours. The specific delay time is set by the 100KΩ potentiometer. If a longer delay is required, a large capacitor can be used instead of the 39nF capacitor. At this time, the delay can reach more than a week.
Adding a positive signal to the trigger output will reset the frequency divider in 4521B.
2. Component selection and production
IC selects MCI4521B integrated circuit; Rl~R4 selects 1/4W metal film resistors; RP selects organic solid variable resistors. C1 selects a ceramic chip capacitor. VD1 selects IN4004 type silicon rectifier diode for use; VD2 selects IN4148 type silicon switch diode for use. VT selects BC337 silicon triode for use; VS selects 1W, 15V silicon Zener diode for use. Connect the circuit as required, and it can work normally without debugging. The delay is reliable and stable, and it is recommended to be powered by a 6-15V regulated power supply.