table of Contents
1. Basic introduction and experimental platform of SDRAM:
3. Introduction of experimental SDRAM:
2. SDRAM—W9812G6KH-6 function description:
1. Basic introduction and experimental platform of SDRAM:
1. Introduction to SDRAM:
Synchronous dynamic random access memory (synchronous dynamic random-access memory, referred to as SDRAM) is a dynamic random access memory (DRAM) has a synchronous interface can be implemented to store and read data. The main attention here is synchronization , dynamic , and random .
Synchronization : SDRAM has a synchronization interface, it will wait for a clock signal before responding to the control input, so that it can synchronize with the computer's system bus. This word is often encountered in FPGA, which reflects the timing requirements that SDRAM must comply with, that is, data and commands are synchronized on the clock.
Dynamic : The storage structure in RAM will be lost when power is turned on, and will also be lost when power is on. Because the data stored in SDRAM is binary data, if it is not 0, then 1. The circuit used to store the binary data is composed of capacitors. Since capacitors are devices that slowly discharge over time, it is necessary to constantly refresh the storage circuit inside to achieve the function of storing data. Compared with the SRAM that can store data without a refresh circuit, there is one more refresh operation in SDRAM, but it can save a lot of cost. Therefore, the selection of the device needs to consider many aspects such as function and cost.
Random : It can be seen from the literal meaning that SDRAM can perform data access operations on the internal address randomly.
2. SDRAM history:
SDRAM has gone through five generations since its development. They are: the first generation SDR SDRAM, the second generation DDR SDRAM, the third generation DDR2 SDRAM, the fourth generation DDR3 SDRAM, and the fifth generation, DDR4 SDRAM.
The first generation of SDRAM uses a single-ended (Single-Ended) clock signal, and the second, third and fourth generations use a differential clock signal that can reduce interference as the synchronization clock because of the faster operating frequency.
The clock frequency of SDR SDRAM is the frequency of data storage. The first-generation memory is named after the clock frequency. For example, pc100 and pc133 indicate that the clock signal is 100 or 133MHz, and the data read and write rate is also 100 or 133MHz.
After the second, third, and fourth generations of DDR (Double Data Rate) memory, the data read and write rate is used as the naming standard, and the symbol representing its DDR algebra is added to the front, PC-that is, DDR, PC2=DDR2, PC3=DDR3 . For example, PC2700 is DDR333, its operating frequency is 333/2=166MHz, and 2700 means that the bandwidth is 2.7G.
The read and write frequency of DDR ranges from DDR200 to DDR400, DDR2 ranges from DDR2-400 to DDR2-800, and DDR3 ranges from DDR3-800 to DDR3-1600.
Many people misunderstand SDRAM as the first generation, which is SDR SDRAM, and it is misleading as a noun.
SDR is not equal to SDRAM.
3. Introduction of experimental SDRAM:
1. Memory architecture
This experiment uses the W9812G6KH-6 SDRAM chip of Winbond Company, and the AC620FPGA development board of Xiaomei Ge. Before writing the SDRAM interface, we must first understand the system architecture and general overview of this SDRAM. The data manual of this type of memory can be downloaded from the Internet: 
Figure 1: IS42S16400F memory architecture
IS42S16400F memory mainly includes instruction decoder, address line, data line, memory block, mode register and dynamic circuit control.
(1) Instruction decoder
The instruction decoder includes clock signal (clk), clock enable (cke) and control instruction signal (cs/ras/cas/we), and the control instruction signal performs a series of control actions on the memory after decoding.
(2) Address line
The address lines include 16-bit row and column address lines and 2-bit block address lines. The row and column address lines are A0-A11, which are multiplexed buses, and row and column addresses are time-division multiplexed. Block address lines ba0 and ba1 select the block ram of the memory.
(3) Data cable
The data line is a 16-bit data bus dq, which is a tri-state signal and is a data interface for data writing and reading.
(4) Storage block
IS42S16400F has four storage blocks, and each block can store data. The storage blocks can be selected through ba0 and ba1.
(5) Mode register
The mode register is to configure the working mode of the SDRAM, read and write mode, burst length, etc.
(6) Dynamic circuit control
These modules mainly include the coding of row and column addresses, self-refresh timing and self-refresh operation.
2. Basic features
(1) Clock frequency: 200, 166, 143MHz)
(2) Complete synchronization, output data at the rising edge of the clock
(3) 3.3V power supply
(4) Programmable conflict length (1,2,4,8, full page)
(5) Every Refresh 4096 times in 64ms
(6) Programmable cas delay (2,3 clock cycles) (I will talk about it later)
(7) Burst read and write or single read and write
(8) Byte is controlled by LDQM and UDQM
(9) Storage capacity 1Mbit * 16bit * 4Bank = 64Mbit
storage depth: IS42S16400F has 4 blocks, row address 12bit, column address 8bit. So each block has 2^12 * 2^8 = 4096 * 256 = 1,048,576
Storage width: 16bit
storage capacity per storage unit : 4 * 1,048,576 * 16 = 64Mbit
2. SDRAM—W9812G6KH-6 function description:
1. General description:
The 64Mb SDRAM is a high-speed CMOS, dynamically designed for 3.3V random access memory, which can store 67,108,864 bits of data. Each 16,777,216-bit storage area is organized into 4,096 rows x 256 columns of storage units, and each unit stores 16-bit data.
64Mb SDRAM includes an automatic refresh mode, power saving and power down modes. All signals are registered on the rising edge of the clock signal CLK.
All inputs and outputs are compatible with LVTTL.
The 64Mb SDRAM has the ability to synchronize conflicts, and starts self-timed line precharge at the end of the burst.
When visiting one of the Banks, pre-charging one bank and the other three banks will hide the pre-charging cycle and provide seamless, high-speed, random access operations.
SDRAM read and write access is burst-oriented, read and write access to the selected location and continue to access the selected location. Before read and write access, an activation command is required, followed by a READ or WRITE command, and the precharge is started after the end. The programmable READ or WRITE burst length includes 1, 2, 4 and 8 positions or full pages, with burst termination options.
2. General working process:
Initialize SDRAM first when powering on. The initialization process includes:
(1) Power on and wait for the clock to stabilize, DQM is high, and CKE is high.
(2) 200μs delay, during which no other commands except No-Operation command are allowed. There is at least one No-Operation command during this period.
(3) Give the PRECHARGE command after 200us. Pre-charge all banks to make all banks in an idle state.
(4) Two automatic refresh operations.
(5) Configuration mode register.
After initialization, the SDRAM is in an idle state, and other operations can be performed on the SDRAM, such as read operations, write operations, and automatic refresh operations. The automatic refresh operation is written in the previous article, refreshing 4096 times every 64ms, that is, refreshing 4096 rows of memory cells every 64ms to prevent data loss. There must be an active command (ACTIVE) before the read and write operations to activate the determined bank and the determined row, and then perform the read and write operations. The precharge command is required after reading and writing.
Pin function introduction:
The following is the IS42S16400F chip pin diagram and pin description table:
A0-A11 (Input): Address input. Samples A0-A11 during the ACTIVE command (row addresses A0-A11) and READ/WRITE commands (A0-A7, where A10 defines automatic precharge) to select a location from the memory array of the corresponding bank. During the PRECHARGE command, A10 is sampled to determine whether to precharge all memory banks (A10 is high) or the memory banks selected by BA0 and BA1 are (LOW). Address input also provides an opcode during the LOAD MODE REGISTER command.
DQ0-DQ15 (Inout): I/O pins. I/O through these pins can be controlled in bytes using the LDQM and UDQM pins.
BA0, BA1 (Input): Bank select address. BA0 and BA1 define the bank to which the ACTIVE, READ, WRITE or PRECHARGE command is being applied.
CLK (Input): CLK is the main clock input of the device. With the exception of CKE, all inputs of the device are synchronized with the rising edge of this pin.
CKE (Input): CKE input determines whether to enable CLK input. The next rising edge of the CLK signal is valid when CKE is high and invalid when it is low. When CKE is LOW, the device will be in power-down mode, clock suspend mode or self-refresh mode. CKE is an asynchronous input.
CS (Input): CS input determines whether command input is enabled in the device. Command input is enabled when CS is LOW, and command input is disabled when CS is HIGH. When CS is high, the device maintains the previous state.
CAS (Input): CAS together with RAS and WE constitute a device command. For detailed information about device commands, see "Command Truth Table" (will be given below).
RAS (Input): RAS, CAS and WE together constitute a device command. For detailed information about device commands, see "Command Truth Table" (will be given below).
WE (Input): WE, together with RAS and CAS, form a device command. For detailed information about device commands, see "Command Truth Table" (will be given below).
LDQM, UDQM (Input): LDQM and UDQM control the low byte and high byte of the I/O buffer. In the read mode, LDQM and UDQM control the output buffer. When LDQM or UDQM is LOW, the corresponding buffer byte is enabled, and when HIGH, it is disabled. When LDQM / UDQM is high, the output enters a high impedance state. This function corresponds to OE in conventional DRAM. In write mode, LDQM and UDQM control the input buffer. When LDQM or UDQM is LOW, the corresponding buffer byte is enabled, and data can be written to the device. When LDQM or UDQM is high, the input data is shielded and cannot be written to the device.
VDDQ (pow): output buffer power supply.
GNDQ (pow): Output buffer ground.
VDD (pow): The internal power supply of the device.
GND (pow): The internal ground of the device.
The following table is the truth table of commands and DQM operations:
The main commands of SDRAM controlled by CS/RAS/CAD/WE are: PRECHARGE, ACTIVE, AUTO_REFRESH, READ, WRITE, No-Operation, Mode Register Set.