timing
Improvement method 1: increase the register level a*2+b*6 to separate multiplication and addition, first multiply and assign to variables and then add can be improved
Improvement method 2: use the parallel structure to split the multiplier into smaller logic periods to realize the function
Improvement method 3: Flatten the logical structure, which is similar to the parallel structure and is specially used for priority coding logic. For example, if elseif is improved into a parallel logical structure that is all if, and the logical structure is flattened.
Improvement method 4: Register balance, A=A1 B=B1 C=C1 D=A+B+C is improved to A=A1+B1 C=C1 D=A+B, and the key path is simplified. Move combinational logic from a critical path to an adjacent path
Improvement method 5: rearrange the path and change the order of if else.
time lag
Removing pipeline registers improves latency, but increases combinational latency between registers.
flow
Breaking up loops can increase traffic at the expense of increasing area proportionally.
Maximum clock frequency: 1 Clock arrival until data reaches Q terminal time 2 Propagation delay between flip-flops 3 Routing delay 4 Setup time
5 Propagation delay of start flip-flop and capture flip-flop