There are many different areas in the IC industry, IC designers will feature somewhat different. A good IC designer in a field may take a long time to become familiar with the field B of knowledge. At the beginning of our careers, we should ask ourselves some questions, we want to be what kind of IC designer? Consumer? PC peripherals? Communication? Microprocessor or DSP? And so on?
IC design rules and the basic process is the same, regardless of what type are added thereto. HDL, FPGA and software are the best tools to help our understanding of the chip. IC soul is knowledge. So the first challenge we face will be designed to obtain relevant information, and understand information and apply it.
But some information is not free, we need to add some association or buy some documents, such as those from the Organization IEEE / ISO and so on. The designer should have a strong background knowledge to quickly understand that they even exist or can improve the standard. A good designer should design should have sufficient knowledge and application of skills and tools they continue to accumulate.
For example: Conversion Ethernet HUB controller 8
Knowledge required: IEEE802.3 standards, including 10MHZ 100MHZ Ethernet and Fast Ethernet.
Related areas: Asynchronous Transfer Mode (ATM), IEEE802.11 wireless LAN, IEEE1394, USB and so on.
HDL, computer simulation and can only solve part of the digital ASIC design flow. If any portion of the analog IC, he will depend analog designer or purchased from another manufacturer. Even some purely digital part but also from some other manufacturers to buy in order to accelerate time to market. Those are not part of our design is called IP, including HDL code, netlist, hard core. For the design of the technology we depend on hard-core. Some IP is very expensive, as in the USB2.0 PHY in. Some small companies do not have enough manpower and software resources to complete some work, even they can not book enough grain shortage in the original period, therefore relates to service companies to replace their work. But not every IP will meet our needs, sometimes we need some changes made after purchase. We want to determine the use to the IPs before designing.
In the beginning of the design, designers must understand all the relevant standards, specifications and algorithm. But there are many ways to apply these standards and algorithms. The best binding structures is fast and minimal chip size. Unfortunately, the rapid demand and needs of the smallest chip size often is contradictory. Therefore, planning an optimal structure is also an important issue in front of HDL coding.
For example: 1: divider
Divisor is fixed. The fastest way is to look-up table, but this method requires large memory. We can continue to subtract the divisor from the dividend until the new dividend is smaller than the divisor. It will take more time but with a minimum of hardware. There are many ways to build a divider, each method has his own advantages and disadvantages.
2: Dynamic evaluation of the image processing
Found in the previous picture most similar 8 × 8 block, the whole movie clip. There are full search and search of the most basic three-step method. Many papers have discussed optimization of hardware complexity and speed of construction, and here I no longer Cheung explained.
A good designer should be ongoing training and practical experience. We have to be very careful and patient in each design work. Because NRE will consume a lot of money, and weeks of time, if he carelessness, the designer will be responsible for the money and the plan failed. Experience and caution is perhaps the best way to complete a successful design project.
The following terms are some suggestions for a steady and successful design :( Perhaps some friends also pointed out that some of them, I am here only a brief description, may be slightly different)
Naming Style:
1 do not use keywords signal names;
2 do not VERILOG signal name with a keyword;
3 meaning named signal;
4 named I / O port with as short name;
5 do not mix with a high and low signal conditions naming;
first letter must be 6 signal AZ is a rule;
7 causes the module name, the same instance name and file name;
Coding Style: Remember, a good code that others can easily read and understand.
1 to increase as much as possible Description Statement;
2 design in a fixed format and encoding module unify all root items from the format defined leader;
3 all designed into different modules or entities suitable number;
4 always in a All signal / process must be relevant;
5 Do not use keywords or some often used to secure a comprehensive grammar;
6 Do not use complex logic;
7 if all the conditions in a statement must be relevant;
design style
1 strongly recommended to use a synchronous design;
2 always keep in mind in the design timing problems;
3 begins to be considered in a design to the ground level or the high level reset, synchronous or asynchronous reset rising or falling edge triggering problems, must comply with it in all modules;
4 if with different situations and case;
. 5 when the latch signal or a bus to be careful;
6 sure that all output signals of the register can be reset / set;
7 never again read any internal memory (e.g., SRAM) before writing
8 different from one another to transfer data clock to clock data buffer, his work as a dual-clock the FIFO;
. 9 may be used in a two-dimensional array in VHDL, it is very useful. In VERILOG he only can be used in the test module can not be comprehensive;
10 to comply with register-in register-out rule;
11 as the synthesis tool synopsys DC is very stable, will not produce any bugs from synthesis tools;
12 ensure that the FPGA and ASIC version version as similar as possible, in particular type SRAM, if the same version is ideal;
13 used in the embedded memory BIST;
14 units and a number of dummy correction circuit is necessary;
15 simple the test circuit is needed, often in a number of test chip modules;
16 unless low-power do not control the clock with the door;
17 do not rely on a script to ensure designed. But some good constraints script can play a better performance (e.g., front to the adder);
18 if enough time, the clock to make more than one substituent with the MUX latches;
19 Do internal tri-state, ASIC need to process the internal bus holder State-Tri;
20 is made in the top level of the pad insertion;
21 caution (such as pull-PAD ability to select, Schmitt trigger, 5 volts breakdown voltage etc.);
22 carefully problems caused by clock bias;
23 do not try to generate a signal half cycle;
24 if plethora of functions to be corrected, a request to make a correction function is a function of a check;
25 are arranged in a calculation equation of the number of bits of each signal is a good habit, even if the synthesis tool can do;
26 Do not use the divider HDL provided;
27 cut unnecessary clock. It will cause a lot of trouble in the design and layout, most FPGA have dedicated clock channel 1-4.