[FPGA] digital traffic light design -Display part

module BASYS_BIGPROJECT_Display
(
input clk,
input [1:0]state,
input [2:0]count,
output [5:0]Trans_light,
output [3:0]Num_choose,
output [7:0]Num_data
);

reg [5:0]reg_light = 0;
reg [3:0]reg_Num_digit = 0;
reg [3:0]reg_Num_choose = 4'b1110;
wire [7:0]Num_data_connect;
wire refresh;

reg [3:0]Data_Main = 0;
reg [3:0]Data_Branch = 0;
//divider for refresh
Freq_divider #(13)play(
    .clk(clk),
    .rst(1'b0),
    .count(refresh)
);
//Decode the digit
Digital_decode decoder(
    .clk(clk),
    .data(reg_Num_digit),
    .Trans_num(Num_data_connect)
    );

//switch the light
always @(posedge clk)
begin
    case(state)
        2'b00:begin
            reg_light <= 6'b100001;
            Data_Main <= 6 - count;
            Data_Branch <= 4 - count;
        end
        2'b01:begin
            reg_light <= 6'b100010;
            Data_Main <= 2 - count;
            Data_Branch <= 2 - count;
        end
        2'b11:begin
            reg_light <= 6'b001100;
            Data_Main <= 4 - count;
            Data_Branch <= 6 - count;
        end
        2'b10:begin
            reg_light <= 6'b010100;
            Data_Main <= 2 - count;
            Data_Branch <= 2 - count;
        end
    endcase
end

//Scanned display for digit
always @(posedge refresh)
begin
    if(reg_Num_choose == 4'b1110)
    begin
        reg_Num_choose <= 4'b1011;
        reg_Num_digit <= Data_Main;
    end
    else
    begin
        reg_Num_choose <= 4'b1110;
        reg_Num_digit <= Data_Branch;
    end
end

assign Trans_light = reg_light;
assign Num_choose = reg_Num_choose;
assign Num_data = Num_data_connect;
endmodule