1. SDRAM control commands

1. Precharge Command (precharge command)

The precharge command is used to precharge or close the activated bank. The pre-charge command is entered when {CS, RAS, CAS, WE}=4'b0010. The precharge command can be used to precharge each bank separately or all banks at the same time. Three address bits. A10, BS0 and BS1 are used to define which bank is to be charged in advance when the order is issued. When A10 is high, all banks are precharged. When A10 is low, BS0 and BS1 select which bank to precharge. After the precharge command is issued, the precharge bank must be reactivated to perform a new read or write access. The delay between the precharge command and the activation command must be greater than or equal to the precharge time (trp).

2. Bank Activate Command (activation command)

The bank activation command must be applied before any read or write operations. The delay from the bank activation command to the start of the first read or write operation cannot be less than the delay time (trcd) from RAS to CAS. Once a bank is activated, it must be precharged before another bank activation command can be issued. The minimum time interval between successive bank activation commands for the same bank is determined by the device's RAS time (trc).

3. Self Refresh Command (self-refresh command)

Before issuing the Self Refresh command, all banks must be idle. Once this command is used, CKE must be kept low to keep the device in self-refresh mode. When SDRAM enters self-refresh mode, all external control signals, except CKE, are disabled. During the internal clock disable period, self-refresh operation to save power. When CKE returns to the high position, the device will exit the self-refresh operation. Any subsequent commands can be issued from the end of the Self Refresh command after txsR. f. In normal operation, the automatic refresh cycle is burst (rather than uniformly distributed), and a burst of 4.096 automatic refresh cycles should be completed after entering and exiting the self-refresh mode.

4. Burst Read Command (conflict read command)

Burst read command: The address input determines the starting column address of the burst. The mode register sets the burst type (sequential or interleaved) and burst length, 1, 2, 4 or full page.

5. Burst Write Command (conflict write command)

Burst write command: address input determines the starting column address. The data of the first burst write cycle must be applied to the DQ pin on the same clock cycle as the write command. The remaining data input must be provided on each subsequent rising clock edge until the pulse length is complete. The data provided to the DQ pin after the conflict is over will be ignored.

6. No Operation Command (no operation command)

When SDRAM is in idle or waiting state, the No Operation command should be used to prevent SDRAM from registering any unnecessary commands between operations. The No Operation command will not terminate the previous operation that is still executing, such as a burst read or write cycle.

7. Mode Register Set (mode register set)

After the initial startup, the mode register setting command must be issued before the device can operate normally. Before issuing the mode register setting command, all banks must be in a pre-charged state, and CKE must be high for at least one cycle. The mode register setting command is activated by the low signal of RAS. The address input data in this cycle defines the parameters to be set, as shown in the mode register operation table. When the delay equal to trsc passes, a new command can be issued according to the mode reqister set command.

8. Other commands

There are other commands. If you don’t list them one by one, just list the ones you want to use and the commonly used ones. See the data sheet for details.