Behavioral modeling has two iconic structures:
initial structure and always structure.
Initial structure and always structure can appear many times in a module, just like data flow modeling assign.
All initial structures and always structures in a module are executed at the same time, and are not distinguished by the order in which they appear in the code. But neither structure supports nesting.
1. Behavior-level modeling syntax
1. Initial structure
initial a = 1;
initial begin
a = 1;
b = 2;
end
2.Always structure
always <时序控制方式> 执行语句
例：
always # a= ~a;
always @(敏感事件)
例
always @(posedge a, negedge b) begin
a = 1;
b = 1;
end
always @(*) ///表示该always结构中所有的事件信息
Example: Level trigger D latch
always@(clk or reset or d)begin
if(reset)
q = 0;
else if(clk)
q = d;
else
end
D flip-flop with asynchronous clear function
always@(posedge clk or negedge reset)begin
if(！ reset)
q = d;
else
q = d;
end
3. There are many blocks in initial and always to make them as a whole. The
sequence is fast
. The beginning
... end content is executed in order. The parallel fast fork...join
content is opened at the same time
begin
#10 a = 1;
#10 b = 1;
#10 c = 1;
end
fork
#10 a = 1;
#20 b = 1;
#30 c = 1;
join
两段代码的执行结果一致
Blocks can be nested
例
begin
a= 0;
fork
#10 b = 1;
#10 c = {a,b};
join
#10 d = {b,a};
end
4. If statement
(1) if (condition) statement;
(2) if (condition) statement_1;
else statement_2;
(3) if (condition_1) statement_1;
else if (condition_2) statement_2;
else statement_3;
If there are many items in the statement after the if, you can use begin···end
Note: Every if has an else, even if the else has no return value, write an empty statement, which makes it easier to understand the code
5, case statement
case (表达式)
分支1：语句1；
分支2：语句2；
default：默认项；
endcase
6, loop statement
while（判断条件)
begin
循环语句；
end
for(初始化条件 ； 判断条件 ； 变量控制)
begin
循环语句；
end
repeat（次数）
begin
循环体语句；
end
repeat （次数）@（posedge clock）
begin
循环体语句
end
//循环n次上升沿
forever #10 clock = ~clock;
等价于
always #10 clock = ~clock； 7. Procedural assignment statement:
Blocking assignment a = 1;
Non-blocking assignment b = 1;
例
initial begin
a = 0;
b = 1;
c = {
a, b};
d = {
b, a};
end
得到的值 a = 0,b = 1,c = 01,d = 10;
initial begin
a <= 0;
b <= 1;
c <= {
a, b};
d <= {
b, a};
end
得到的值 a = 0,b = 1,c d 未知，取决于a b之前的数值2. Behavioral level modeling
1.
RTL simulation circuit diagram of four-bit full adder
module add4(A,B,CIN,COUT,S);
input [3:0] A, B;
input CIN;
output [3:0] S;
output COUT;
reg COUT;
reg [3:0] S;
always @(*)begin
{
COUT, S} = A + B + CIN;
end
endmoduleThe simulation effect is shown in the figure
2. The
RTL circuit diagram of the simple ALU circuit is shown in the figure
module ALU(out, a, b, select);
input [7:0] a, b;
input [2:0] select;
output [7:0] out;
reg [7:0] out;
always @(*) begin
case (select)
3'b000: out = a;
3'b001: out = a + b;
3'b010: out = a > b;
3'b011: out = a * b;
3'b100: out = a / b;
3'b101: out = a % b;
3'b110: out = a << 1;
3'b111: out = a >> 1;
default: out = 8'b00000000;
endcase
end
endmoduleThe simulation circuit diagram is shown below
3. Decimal counter
The RTL circuit diagram is shown in the figure
/*完成的功能主要是实现74ls160的功能
reset 异步复位端，上升沿有效，完成复位功能
load 同步置数端，高电平有效，完成置数功能
clock 时钟端口
en 使能端，优先级在reset，load之后，暂停计输
D 同步置数的数据输入端
Q 计数器数据输出端
C 进位输出端
*/
module counter160(clock, reset, load, en, D, Q, C);
input clock, reset, load, en;
input [3:0] D;
output [3:0] Q;
output C;
reg [3:0] Q ;
always@(posedge reset or posedge clock)begin
if(reset == 1)
Q <= 4'd0;
else if(load == 1)
Q <= D;
else if(en)
Q <= Q;
else if(Q == 9)
Q <= 0;
else
Q <= Q + 1;
end
assign C = (Q == 9);
endmodule
4.
RTL circuit diagram of D flip-flop triggered by falling edge
module mydff(Q, Qbar, D, clock);
input D, clock;
output Q, Qbar;
reg Q, Qbar;
always@(negedge clock) begin
Q <= D;
Qbar <= ~D;
end
endmodule
The simulation results are shown in the figure
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