[Basics of MCU] (1) Interpretation of AND gate, OR gate, NOT gate, and NAND gate from the perspective of hardware

1. High level and low level In a
digital circuit, the level used by the circuit composed of TTL electronic components. The level is a voltage range, and it is specified that the output high level is >2.4V, and the output low level is <0.4V. At room temperature, the general output high level is 3.5V, and the output low level is 0.2V. Minimum input high level and low level: input high level>=2.0V, input low level<=0.8V, noise tolerance is 0.4V.

2. AND gate The
AND gate is shown in the figure. It is a circuit composed of diodes and resistors, where A and B are the input terminals, and Y is the output terminal. The +5V voltage is divided by R1 and R2, and a 3V voltage is obtained at point E.

3. Working principle
1. When a low level (0V) is input at both ends of A and B at the same time, since the voltage at point E is 3V, the diodes VD1 and VD2 are all turned on, and the voltage at point E immediately drops to 0.7V (low level) ), that is, when both A and B terminals input low level "0", Y terminal outputs low level "0".
2. When the A terminal inputs a low level (0V) and B terminal inputs a high level (5V), since the voltage at point E is 3V, the diode VD1 is turned on immediately, and the voltage at point E drops to 0.7V. At this time, the positive terminal voltage of VD2 is 0.7V, the negative terminal voltage is 5V, and VD2 is in the cut-off state, that is, when the A terminal inputs a low level "0" and the B terminal inputs a high level "1", the Y terminal outputs a low level "0".
3. When terminal A inputs high level (5V) and terminal B inputs low level (0V), VD1 is cut off, VD2 is on, and the voltage at point E is 0.7V (low level), that is, when terminal A inputs high level When level "1" and low level "0" are input at B terminal, Y terminal outputs low level "0".
4. When both ends A and B input high level (5V) at the same time, neither VD1, VD2 can be turned on, and the voltage at point E is 3V (high level), that is, when both ends of A and B input high level "1" ", the Y terminal outputs "1".
It can be seen that the characteristics of the AND gate are: Only when the input terminals are input high level, the output terminal will output high level; as long as one input terminal inputs low level, the output terminal will output low level.

4. Truth
table The truth table is a table that lists various input values and corresponding output values of the circuit. It enables people to visually see the relationship between the input and output of the circuit. The following table is the truth table of the above AND gate

5. Logic Symbol The
AND gate is composed of 4 components, which is very inconvenient in drawing and analysis. For this reason, a simple symbol can be used to represent the entire AND gate, which is called a logic symbol. The logic symbols of the AND gate are shown in Figure 1-7. The old symbols refer to the symbols used in the early days, the commonly used symbols refer to the symbols used in some countries, and the new standard symbols refer to the latest standard symbols published by my country.

One One One One One One One One One One One One One One One One One One One One One One One One One One One One One
The Truth Table And The Logical Symbols Of The OR Gate