FPGA study notes _SPI protocol

FPGA study notes

SPI protocol

1. SPI协议概念
2. SPI协议原理

1. SPI protocol concept
SPI : short for Serial Peripheral Interface, it is a high-speed, full-duplex, and synchronous communication bus.

Features : One master and multiple slaves, high-speed (up to tens of Mbps), full-duplex, synchronous communication bus, the maximum clock frequency is 1/2 of the system clock frequency, when communicating with another very high-speed SPI device , The maximum clock frequency of SPI may restrict its transmission rate.

Advantages : Only four wires are occupied on the pins of the chip, which saves the pins of the chip, and at the same time saves space and provides convenience for the layout of the PCB.

Application : EEPROM, FLASH, real-time clock, AD converter, digital signal processor and digital signal decoder.

2. SPI protocol principle
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4 modes (MODE1~4) :

(Polarity) CPOL =0/1: Determine the effective level of the clock,
(Phase) CPHA=0/1: Determine the edge of data sampling and transmission.

CPOL =0: SCK idle state is 0, effective state is high level
CPOL =1: SCK idle state is 1, effective state is low level
CPHA =0: collect data at the first edge of the clock
CPHA =1 : Collect data on the second transition edge of the clock
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  • MODE0 : CPOL=0, SCLK changes from low level to high level, CPLA=0, collect data at the first transition edge, and send data at the second transition edge;
  • MODE1 : CPOL=0, SCLK transitions from low to high, CPHA =1: collect data on the second transition edge of the clock, and send data on the third transition edge;
  • MODE2 : CPOL=1, SCLK changes from high level to low level, CPLA=0, collect data on the first transition edge, and send data on the second transition edge;
  • MODE3 : CPOL=1, SCLK changes from high level to low level, CPHA =1: collect data on the second transition edge of the clock, and send data on the third transition edge;

How to determine the working mode between master and slave :

  • If it is a sensor, there will be a datasheet, which clearly indicates its working mode and transmission timing, which can be determined according to requirements;

  • If the master-slave is MCU, the master-slave program is determined by ourselves, and the transmission can be determined by ourselves, but the two MCUs must use the same mode to set;

Compare UART :

advantage:

  1. SPI has a relatively high communication rate, ranging from several megabytes to several tens of megabytes.
  2. The clock can be synchronized, and the error rate of the bus is low.
  3. UART is one-to-one, and SPI can be one-to-many.

Disadvantages: different slaves need to process chip select lines, which is more troublesome.


[Note]: Personal study notes, if there are any mistakes, please feel free to enlighten me. This is polite~~~


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Origin blog.csdn.net/weixin_50722839/article/details/113870248