FPGA study notes _IIC protocol

FPGA study notes

IIC protocol

1. IIC协议概念
2. IIC协议原理
	2.1. 起始位，结束位
	2.2. 器件地址
	2.3. 存储器地址
	2.4. 应答位
	2.5. 读写时序

1. IIC protocol concept
IIC : inter integrated circuit BUS, integrated circuit bus, is a serial communication bus, mostly master-slave structure. Generally used in small data bright occasions, the transmission distance is short.
Features :

• Simple connection : On the physical layer, the IIC protocol has only 2 bus lines: SCL (serial clock line), SDA (serial data line)
• Two-way communication : Two lines can complete the incoming and outgoing of data.
• Multi-master and multi-slave : Multiple masters and multiple slaves can be connected to one IIC bus. At the same time, only one host can initiate a transfer to the bus.
• Fast transmission speed : 100kbit/s in standard mode, 400kbit/s in fast mode, and 3.4Mbit/s in high-speed mode. Two-way data transmission between master and slave devices in bytes.
• Unique ID : Every device on the bus has a unique ID. Only when the transmission on the bus matches the ID of the device, the device responds to the transmission on the bus. There will be no conflicts.

2. Principles of IIC Protocol

• 2.1 Start bit, end bit
  
  Start bit : when the SCL signal is high, SDA appears a falling edge  start data transmission
  stop bit : SCL high level, SDA rising edge  stop data transmission
  bus idle state : SCL high level ; SDA high level;
  SCL high level : SDA data is stable; SCL low level: SDA data changes

• 2.2. Device address
  
  Transmission sequence: from high to low
  Eg. Chip select bits: 3'b100
  Read: 1010_100_1
  Write: 1010_100_0

• 2.3. Memory address
  
  Length: 1 or 2 bytes (related to the number of storage units of the device)
  Location: After the host receives the ACK, the host sends out the storage address

• 2.4. Acknowledge bit
  
  When the sender (picture: master) finishes sending 8-bit data, it waits for the receiver (picture: slave) to send a reply signal to indicate whether the data has been received. 0: answer, 1: not answer. (The response signal is the clock cycle immediately after the 8-bit data is sent (Figure: #9))

• 2.5. Read and write timing

1. Read operation : the complete timing sequence of the host computer reads one (multiple) bytes of data from the specified storage address of the specified slave on the bus :
   ① The host sets SDA as an output;
   ② The host initiates a start signal;
   ③ The host transmits Device address byte, where the lowest bit is 0, indicating a write operation;
   ④ The host sets SDA as a tri-state gate input and reads the response signal from the slave;
   ⑤ Reads the response signal successfully, the host sets the SDA output, and transmits a 1-byte address Data;
   ⑥ The host sets SDA as a tri-state gate input, and reads the response signal from the slave;
   ⑦ When the response signal is successfully read, the host sets the SDA output. For a two-byte address segment device, transfer the low byte address number
   ⑧ data; for 1 Byte address segment devices, without this step;
   ⑨ The host initiates a start signal;
   ⑩ The host transmits the device address byte, the lowest bit is 1, indicating a read operation;
   ⑪ Set SDA as a tri-state gate input, read the response from the slave Signal;
   ⑫ The response signal is read successfully, the host sets SDA as a three-state gate input, and reads one byte of data on the SDA bus.
   ⑬
   Generates no response signal (high level) (no need to set to output high level) , Because the bus will be automatically pulled high);
   ⑮ The host generates a STOP bit to terminate the transmission.

2. Write operation : the complete sequence of the master write one ((multiple)) designated data on the bus to the designated out address of the designated slave.
   Master operation process:
   ① The master sets SDA as output;
   ② The master initiates the start signal;
   ③ The master transmits the device address Byte, the lowest bit of which is 0, indicating a write operation;
   ④ The host sets SDA as a tri-state gate input and reads the response signal from the slave;
   ⑤ When the response signal is read successfully, the host sets SDA as an output, and transmits 1 byte of address data ;
   ⑥ the SDA host tristate gate input, read slave response signal;
   ⑦ successful read response signal, the low byte addresses for two device, transmit the address data byte, 1 byte for the address field device, the host arranged SDA is the output, which transmits the data to be written;
   ⑧ Set SDA as the tri-state gate input, read the slave response signal, for the two-byte address segment device, proceed to step 9; for the 1-byte address segment device, jump directly
   Go to step 11; ⑨ Read the response signal successfully, the host sets SDA as output, and transfer the data to be written (for two-byte address segment devices);
   ⑩ Set SDA as the three-state gate input, read the slave response signal (two Byte address segment device);
   ⑪ When the response signal is read successfully, the host generates the STOP bit to terminate the transmission.

---

Reference materials: "FPGA System Design and Verification Practical Guide"

[Note]: Personal study notes, if there are any mistakes, please feel free to enlighten me. This is polite~~~

---