STA Environment - Timing Path

Introduce how to implement STA constraints on various timing paths in digital design.

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Timing path: The signal starts from the D terminal of the launch flip-flop (Launch Flip-Flop) and ends at the D terminal of the capture flip-flop (Capture Flip-Flop).

Note that "initiating" and "triggering" are not absolute. It must be relative to a certain timing path to determine whether the trigger initiates data or captures data.

For digital circuits, timing paths that require STA analysis include

1. input2reg: From the circuit input terminal to the D terminal of the first-stage flip-flop, combined logic, as shown in the figure below path 1
2. reg2reg: Initiating flip-flop CK to capture flip-flop D in the circuit, sequential logic, path 2 as shown in the figure below
3. reg2output: from the flip-flop CK terminal to the output terminal in the circuit, sequential logic, path 3 as shown in the figure below
4. input2output: from the circuit input to the circuit output, combinational logic, as shown in path 4 as shown below

The timing check is aimed at the above timing paths. Obviously, the most representative timing path is the second flip-flop to flip-flop path.

● Maximum/small timing path: refers to the timing path with the largest/smallest signal delay in the entire circuit.

1. Enter the pathset_input_delay

Specifies the arrival time of data at the input port relative to a certain clock edge (the default is rising edge)

For example, in the figure below, DUA on the right represents the design interior, and INP1 is the design port.

You can specify when INP1 transmits data compared to the rising edge of the clock CLKA, that is, the input delay is $T_{CLKA2UFF0}+T_{CK2Q}^{UFF}+T_C$, can be used to perform STA on UFF1

Use the following SDC command to specify the input delay, -max means the longest path input delay (for setup time check), -min means the shortest path input delay (for hold time check), if not written, it means the definite time

# 周期: 10ns
# 占空比: 50%
# 端口: CLKA
create_clock -period 2 [ get_ports CLKA]

# 每个时钟CLKA上升沿之后最长路径延迟1.5ns、最短路径延迟1ns，INP1端口传入数据
set_input_delay -clock CLKA -max 1.5 [ get_ports INP1]
set_input_delay -clock CLKA -min 1 [ get_ports INP1]

# 每个时钟CLKB上升沿之后6.7ns，INP2端口传入数据
set_input_delay -clock CLKB 6.7 [ get_ports INP2]

2. Output pathset_output_delay

Specify the output time that the output port data should meet relative to a certain clock edge (the default is the rising edge)

For example, in the figure below, DUA on the right represents the inside of the chip, and OUTB is the chip port. The output delay is actually a difference, that is, $T_{C2}-T_{OUTC2UFF1}+T_{setup}^{UFF1}/-T_{hold}^{UFF1}$

-max corresponds to the longest path delay used for setup time checking

-min is used when the delay of the most end path is used, and it is used for keeping time check

# 时钟CLKQ上升沿驱动，用于建立时间检查的外部路径延迟差为5ns
set_output_delay -clock CLKQ -max 5 [ get_ports OUTB]

# 时钟CLKQ上升沿驱动，用于保持时间检查的外部路径延迟差为1.5ns
set_output_delay -clock CLKQ -min 1.5 [ get_ports OUTB]

4. Cross-clock domain paths

● Clock domain (clock domain): A group of flip-flops driven by the same clock is the same clock domain.

● Crossing clock domains: That is, there is a data path from the flip-flop Q terminal of one clock domain to the D terminal of another clock domain.

There are multiple constraint methods for cross-clock domain paths. If multiple constraint methods overlap in the SDC, the constraint with the highest priority takes effect. As shown in the figure below, the more specific the constraint, the higher the priority.

4.1. Timing Exception Pathset_false_path

Since the relationship between the two clocks is uncertain, the signal transmission will inevitably fail to meet the setup time and holdup time. Therefore, when doing STA, you can use the set_false_pathsetting false path to not analyze such a path.

# 从USBCLK时钟域到MEMCLK时钟域的所有时序路径均不作STA
set_false_path -from [get_clocks USBCLK] -to [get_clocks MEMCLK]

Cross-clock domain behavior will lead to metastable problems, so it is generally necessary to synchronize through synchronizers, asynchronous FIFOs, and other methods.

4.2. Path between pins set_max_delay,set_min_delay

Used to specify the maximum and minimum delay between any two pins, not between flip-flops

set_max_delay 5.0 -to UFF0/D
set_max_delay 0.6 -from UFF2/Q -to UFF3/D
set_max_delay 0.45 -from UMUX0/Z -through UAND1/A -to UOR0/Z
set_min_delay -from U1/S -to U2/A 0.6
set_min_delay -from [get_clocks PCLK] -to [get_pins UFF/*/S]

4.3. Multi-cycle pathsset_multicycle_path

Detailed explanation of multicycle path and set_multicycle_path
The explanation of set_multicycle_path in sdc is explained in a simple and simple way
, and set_multicycle_path is thoroughly explained, so as to thoroughly master it
Verilog's ten basic skills 9 (Multicycle Paths)

5. Constant portset_case_analysis

Certain pins of the specified chip are constant level.

In addition to not having to report any irrelevant paths, this also helps reduce the analysis space. Use set_case_analysis constraints to specify such constant signals.

set_case_analysis 0 TEST
set_case_analysis 0 [get_ports {
    
    testmode[3]}]
set_case_analysis 0 [get_ports {
    
    testmode[2]}]
set_case_analysis 0 [get_ports {
    
    testmode[1]}]
set_case_analysis 0 [get_ports {
    
    testmode[0]}]

If the design has multiple functional modes and only one of them needs to be analyzed, set_case_analysis can be used to analyze only a certain value of a certain port.

# 只考虑func_mode == 3'b101的情形
set_case_analysis 1 func_mode[0]
set_case_analysis 0 func_mode[1]
set_case_analysis 1 func_mode[2]