FPGA study notes _ROM core call and debugging

FPGA study notes

ROM core call and debugging

1. ROM存储器IP核的使用
2. 创建.mif文件
3. In system memory content editor内存查看工具的使用
4. Signal tapII工具使用
5. Verilog 代码
6. Modelsim仿真
7. FPGA板级验证

ROM core call and debugging

• Goal: call the ROM core provided in the Quartus software and perform system design
• Phenomenon: A set of data (triangular waveform table) is stored in the on-chip rom built with the IP core in the FPGA. After the development board is powered on, the system starts to read data from the rom and outputs the data directly through the parallel port. Capture the data of the parallel port in real time through the signal tap II software and display it (triangular waveform). Then use the in system memory content editor tool provided in the quartus software to change the data (sine waveform) in the rom online, and then observe the waveform data captured by the signal tapII tool again
• Knowledge points:

1. Use of ROM memory IP core
   Create .mif file
2. Use of In system memory content editor memory viewing tool
3. The Signal tapII tool uses
   an embedded logic analyzer/on-chip logic analyzer, which can directly capture chip node data or external IO port data, and connect to the PC through the JTAG port. The quaturs software on the PC provides the signal tap II software, which communicates with the on-chip logic analyzer through the JTAG line, and sends the node information in the design captured by the on-chip logic analyzer to the PC in real time, and the PC uses the singal Tap II The software displays the data.

1. The use of ROM memory IP core

• (1). IP Catalog, search for ROM, double-click ROM: 1-port, set data width, rom memory and other information according to requirements, click next

• (2). Select the register port according to your needs, click next

• (3). Select the .mif file and click next

• (4). Click next

• (5). Click finish

• (6). Generate .qip file, right click, set as top level entity, analysis and synthesis

• (7). Writing testbench, simulation verification function

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2. Create .mif file

• (1). Create a new file, select memory initialization file, and click OK

• (2). Set the bit width and memory depth, click OK to generate the following file

• (3). After changing the memory value as required, click file, save as, set the name, save the .mif file in the project folder, and the .mif file setting is complete

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3. Use of in system memory content editor memory viewing tool

• (1). tool–>in system memory content editor

• (2). The following interface is displayed, click read to read the data in the rom

• (3). Right click on rom and select import data from file

• (4). Select the edited .mif file and click open

• (5). Click Write, the data in the file will be written into the rom

• (6). The written data is displayed in signal tapII

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4. Use signal tapII tool

• (1). To create a new file, click signal tap logic analyzer file

• (2). Add clk signals in order

• (3). Add signals to be observed in order

• (4). After the setting is completed, click file, after setting the name and path, save

• (5). According to the design, set the depth of the storage area and generate the .stp file

• The logic analyzer ensures that the sampling clock is higher than the rate of the signal to be sampled
• Sample depth: The depth of the
  memory. The captured data is equivalent to an internal memory. Continuous capture requires observation data. Because the speed is very fast, all the data to be observed must be stored in the memory first, and then from the memory Send it to the computer via the JTAG cable for real-time display; otherwise, because the JTAG itself is not very high speed, it is impossible to transmit 50MHz directly sampled data, use this storage method to reduce the speed

• (6). Run the logic analyzer in the following order

• (7). Continuous real-time detection data

• (8). Set the real-time data format to line graph display, the shape is as follows

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5. Verilog code

//----top---------------------------------------
module rom_top(

	input clk,
	input rst_n,
	output [7:0] q
);

	reg [7:0] addr;

rom uut(
		.address(addr),
		.clock(clk),
		.q(q)
	);

	always@(posedge clk or negedge rst_n)
		if(!rst_n)
			addr <= 8'd0;
		else
			addr <= addr + 8'd1;
endmodule

//----testbench------------------------------
`timescale 1ns/1ns
`define clock_period 20

module tb_rom;
	reg clk;
	reg [7:0] addr;
	wire [7:0] q;

	rom uut(
		.address(addr),
		.clock(clk),
		.q(q)
	);
	integer i;
	initial clk = 1;
	always #(`clock_period/2) clk = ~clk;
	
	initial begin
		addr =8'd0;
		for(i=0;i<2550; i=i+1)begin
		#(`clock_period);
		addr = addr + 8'd1;
		end
		#(`clock_period*50);
		$stop;
	end
endmodule

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6. Modelsim simulation

• Simulation waveform debugging
  Right-click the signal, select format–>analog (automatixc), and convert the signal value to an analog value

• Triangle waveform

• Sine wave

4. FPGA board-level verification

• The waveform is converted from a triangle to a sine shape

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[Note]: Personal study notes, if there are any mistakes, please feel free to enlighten me. This is polite~~~

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