FPGA self-study notes--the use of DDS ip core (vivado)

For learning records.

1. The concept of DDS

DDS (Direct Digital Frequency Synthesizer) Direct Digital Frequency Synthesizer This article mainly introduces how to call Xilinx's DDS  IP core to generate Sin and Cos signals of a certain frequency.

2. Frequency selection

Open the IP core configuration, parameter Selection select System Parameters, there are two options,

When System Parameters is selected, the output frequency can be directly input in the IP core.

When selecting Hardware Parameter, it can be determined by inputting the frequency control word PINC in the IP core or in the program.

As shown in the picture,

The PINC selected is 1101000110110111 = 53687

By the manual formula,

 

 f = （53687*100*10^6）/(2^16) = 81.91986 MHz

Let's look at the information of the IP core again.

 In addition, we can also control the PINC in the program.

top.v is as follows.

`timescale 1ns / 1ps

module sin_20M(
    input clk,
    input config_tvalid,
    input rst_n,
    input [15:0]        config_data_poff,config_data_pinc,
    output [7:0]       dds_data_sin_0,dds_data_cos_0
    );
   wire m_axis_data_tvalid;
   wire m_axis_phase_tvalid;
   wire [15:0]m_axis_phase_tdata;
  dds_compiler_0 dds_init (
  .aclk(clk),                                  // input wire aclk
  .s_axis_config_tvalid(config_tvalid),  // input wire s_axis_config_tvalid
  .s_axis_config_tdata({16'd0,config_data_pinc}),    // input wire [31 : 0] s_axis_config_tdata
  .m_axis_data_tvalid(m_axis_data_tvalid),      // output wire m_axis_data_tvalid
  .m_axis_data_tdata({ dds_data_sin_0,dds_data_cos_0}),        // output wire [15 : 0] m_axis_data_tdata
  .m_axis_phase_tvalid(m_axis_phase_tvalid),    // output wire m_axis_phase_tvalid
  .m_axis_phase_tdata(m_axis_phase_tdata)      // output wire [15 : 0] m_axis_phase_tdata
);

endmodule

 tb file is as follows.

`timescale 1ns / 1ps
//

// 该tb文件中直接输入控制字 66 ----6666
//  f=(PINC*fclk)/(2^phase width)=6666乘100000000/2的16次方=10.17MHz
//


module sintb(
    );
    reg clk;
    always #5 clk<=~clk;
    reg     rst_n;
wire [7:0]       dds_data_sin_0,dds_data_cos_0;
reg [15:0]        config_data_pinc,config_data_poff;
reg               config_tvalid;
sin_20M     dds_001_Init
(
    .clk(clk),
    .rst_n(rst_n),
    .dds_data_sin_0(dds_data_sin_0),
    .dds_data_cos_0(dds_data_cos_0),
    .config_data_poff(config_data_poff),
    .config_data_pinc(config_data_pinc),
    .config_tvalid(config_tvalid)
);
initial
begin
    clk = 0;
    rst_n = 1;
    config_data_poff = 16'h4000;
    config_data_pinc = 16'd66;
    config_tvalid = 1'b1;
    #100000
    config_data_pinc = 16'd6666;
    #100000
    config_data_poff = 16'h8000;
    $stop;
end
endmodule

 output waveform.

Complete project: https://download.csdn.net/download/lgk1996/83163014