1. Blocking and non-blocking:
1. The execution of blocking assignment can be regarded as an operation with only one step, that is, calculating the value of RHS and updating LHS, at this time, no interference from other statements is allowed. Symbol =
2.
Non-blocking assignment is determined by the clock beat. When the clock rises, the right side of the assignment statement is executed, and then all assignment statements between begin-end are assigned to the left side of the assignment statement at the same time.
The difference between assign statement and always
The assign statement cannot be used with a clock.
The always statement can be with or without clock. When always without a clock, the logic function and assign are exactly the same, and only generate combinational logic. The assign statement is recommended for simple combinational logic, and the always statement is recommended for more complex combinational logic.
Latch
refers to the latch
A memory cell circuit sensitive to pulse level. Both latches and registers are basic storage units, latches are level-triggered memories, and registers are edge-triggered memories. The basic functions of the two are the same, and both can store data. Latches are generated by combinational logic, while registers are used in sequential circuits and generated by clock triggers.
The main hazard of latches is glitch. In the design, the use of latches should be avoided as much as possible.
Two reasons for the occurrence of latches in the code are the incomplete description of if or case statements in combinatorial logic. For example, if lacks the else branch and case lacks the default branch, latches appear in the code synthesis process. The solution is that if must bring the else branch, case must bring the default branch.
It should be noted that only the if or case statement of the always statement without the clock is incomplete will produce the latch, and the statement of the if or case statement with the clock will not produce the latch if the statement is incomplete.
state machine
Mealy
state machine : The output of combinational logic not only depends on the current state, but also on the input state.
Moore
state machine : The output of combinational logic only depends on the current state.
Three-stage state machine:
One-stage: The entire state machine is written into an always module, in which the state transition is described as well as the input and output of the state. This kind of state machine is not recommended , because in terms of code style, it is generally required to separate combinational logic and sequential logic; in terms of code maintenance and upgrade, the combination of combinational logic and sequential logic is not conducive to code maintenance and modification. It is also not conducive to restraint.
Two-stage: Two always modules are used to describe the state machine. One always module uses synchronous timing to describe state transition; the other module uses combinational logic to determine state transition conditions, and describes state transition rules and outputs. Different from the one-stage state machine, it needs to define two states, the current state and the second state, and then realize the sequential logic through the conversion of the current state and the second state.
Three-stage: Based on the two always module description methods, three always modules are used, one always uses synchronous timing to describe state transition, one always uses combinational logic to determine state transition conditions and describes state transition rules, and the other always describes state transition conditions. Status output (can be output by combinational circuit or output by sequential circuit).
The basic format of a three-stage state machine is:
The first always statement realizes the synchronization state jump;
The second always statement uses combinational logic to determine the state transition conditions;
The third always statement describes the state output (can be output by combinational circuit or output by sequential circuit).
Before writing the state machine code, generally draw the state transition diagram first, so that the idea will be clearer when writing the code
Let's take a divide by 7 as an example
1 module divider7_fsm (
2 //系统时钟与复位
3 input sys_clk ,
4 input sys_rst_n ,
5
6 //输出时钟
7 output reg clk_divide_7
8 );
9
10 //parameter define
11 parameter S0 = 7'b0000001; //独热码定义方式
12 parameter S1 = 7'b0000010;
13 parameter S2 = 7'b0000100;
14 parameter S3 = 7'b0001000;
15 parameter S4 = 7'b0010000;
16 parameter S5 = 7'b0100000;
17 parameter S6 = 7'b1000000;
18
19 //reg define
20 reg [6:0] curr_st ; //当前状态
21 reg [6:0] next_st ; //下一个状态
22
23 //*****************************************************
24 //** main code
25 //*****************************************************
26
27 //状态机的第一段采用同步时序描述状态转移
28 always @(posedge sys_clk or negedge sys_rst_n) begin
29 if (!sys_rst_n)
30 curr_st <= S0;
31 else
32 curr_st <= next_st;
33 end
34
35 //状态机的第二段采用组合逻辑判断状态转移条件
36 always @(*) begin
37 case (curr_st)
38 S0: next_st = S1;
39 S1: next_st = S2;
40 S2: next_st = S3;
41 S3: next_st = S4;
42 S4: next_st = S5;
43 S5: next_st = S6;
44 S6: next_st = S0;
45 default: next_st = S0;
46 endcase
47 end
48
49 //状态机的第三段描述状态输出（这里采用时序电路输出）
50 always @(posedge sys_clk or negedge sys_rst_n) begin
51 if (!sys_rst_n)
52 clk_divide_7 <= 1'b0;
53 else if ((curr_st == S0) | (curr_st == S1) | (curr_st == S2) | (curr_st == S3))
54 clk_divide_7 <= 1'b0;
55 else if ((curr_st == S4) | (curr_st == S5) | (curr_st == S6))
56 clk_divide_7 <= 1'b1;
57 else
58 ;
59 end
60
61 endmodule
Modular design
Generally adopt top-down design
File can be in the top TOP
Example facilitator module
The left side of the figure above is the definition of sub-modules, various input and output interfaces
The right side of the above figure corresponds to the instantiation of the top-level module, which includes the sub-module name. The instantiated module name (you can write it at will, we generally name it as u_+sub-module name). The sub-module port needs to be consistent with the sub-module function port. The instantiated module port is consistent with the port definition of the TOP layer, that is, the corresponding connection is made
The instantiation of the parameter, the instantiation of the parameter is based on the module instantiation, adding the signal definition of the parameter, as shown in the following figure:
When instantiating the parameters, add "#" after the module name to indicate that the parameter list is followed. The MAX_NUM defined by the timing module and the TIME_SHOW of the top-level module are both equal to 25000_000. When TIME_SHOW=12500_000 is defined in the top-level module, then the value of MAX_NUM of the sub-module is actually equal to 12,500_000. Of course, even if the sub-module contains parameters, it is not necessary to add the instantiation of the parameters when the module is instantiated. In this case, the parameter value of the sub-module is equal to the value actually defined inside the module.
The meaning of localparam in Verilog grammar is also parameter definition. The usage is basically the same as parameter. The difference is that the parameter defined by parameter can be instantiated, while the parameter defined by localparam refers to the local parameter . The upper module cannot do the parameter defined by localparam. Instantiate